- SDTV/HDTV serial digital video standard compatible
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Supports 270 Mbps, 360 Mbps, 540 Mbps, 1.4835Gbps combine 1.485 Gbps The data transfer rate of SDV is automatically detected
- Low output jitter: 125ps max, 85ps typical
- Low power consumption: 430mW typical
- No external serial data rate setting or VCO filter element required*
- 快速PLL锁定时间：
- Adjustable depth-timed alignment video FIFO
- Built-in Self-Test (BIST) and Video Test Pattern Generator (TPG)*
- Automatic EDH/CRC word and markup generation with insertion
- On-chip auxiliary data FIFO and insertion control circuitry
- Flexible control and configuration of I/O ports
- LVCMOS compatible data and control inputs and outputs
- 75Ω ECL compatible, differential, serial cable driver output
- 3.3VI/O power supply and 2.5V logic power supply operation
- 64-pin TQFP package
*Patent application has been obtained or is pending.
illustrate
LMH0030 SMPTE 292M/259M Digital & Auxiliary Data FIFO & Integrated Cable Driven Video Serializer is a monolithic integrated circuit that encodes, serializes and transmits bits of parallel digital video data that meets SMPTE 125M and 267M standard definition, 10-bit wide component video and SMPTE 260M, 274M, 295M and 296M high definition, 20-bit wide component video standards. LMH0030 works at SMPTE 259M serial data rates 270 Mbps , 360 Mbps for SMPTE 344M serial data at 540 Mbps, and SMPTE 292M serial data and 1.485 Gbps at 1483.5 Mbps. Serial data clock frequencies are generated internally and do not require external frequency setting, trimming or filtering elements.
The functions performed by LMH0030 include: parallel-to-serial data conversion, SMPTE standard data encoding, NRZ to NRZI data format conversion, serial data clock generation and serial data, automatic detection of video rates and formats, accessory packet encoding and management of insertion and serial data output drivers. Whereas LMH0030 has automatic EDH/CRC word and logo generation and per SMPTE RP-165 (standard definition) or SMPTE 292M (high definition) insertion circuitry Optional LSB jitter is implemented to prevent the generation of pathological patterns. What makes LMH0030 unique is its FIFO for video and ancillary data. Video FIFO allows video data to be delayed from 0 to 4 parallel data video timing clock cycles. Ports and on-chip FIFO and control circuitry and insert storage space auxiliary data auxiliary flags, packets and checksum auxiliary data. LMH0030 also has an exclusive built-in Self-Test (BIST) and Video Test Mode Generator with SD and HD Component Video Test Modes (TPG): in 4:3 and 16:9 reference black, PLL and EQ pathologicals and color bars for NTSC and PAL standard raster formats*. Color bar pattern with optional bandwidth limit encoding in chroma and luminance conversion.
Whereas LMH0030 has a unique multi-function I/O direct access control and configuration setup port. The port can be programmed to provide external access control functions and input/output metrics. As a result, designers can customize LMH0030 to suit the desired application. Commands after power-up or reset LMH0030 automatically configured to the default running state. For output drivers, PLL and serial independent power pins improve power rejection, output jitter, and noise performance.
While the LMH0030 is powered by an internal circuit, +2.5 V and I/O circuits from a +3.3 V supply. Typical power consumption of 430mW at 1.485 Gbps includes two 75Ω AC-coupled and back-end matched output loads. The device uses a 64-pin TQFP.
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- The SDTV/HDTV parallel-to-serial digital video interface is:
- camera
- vcr
- Telecines
- Digital video routers and switches
- Digital video processing and editing equipment
- Video test pattern generator and digital video test equipment
- Video signal generator
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