- SDTV/HDTV serial digital video standards compatible
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Supports 270 Mbps, 360 Mbps, 540 Mbps, 1.4835Gbps combine 1.485 Gbps SDV's data transfer rate is automatically detected
- Low output jitter: 125ps maximum, 85ps typical
- Low power: 430mW typical
- No external serial data rate setting or VCO filtering components required*
- Fast PLL lock time:
- Adjustable depth, timing, and line video FIFO
- Built-in self-test (BIST) and video test pattern generator (TPG)*
- Automatic EDH/CRC word and marker generation and insertion
- On-chip auxiliary data FIFO and insertion control circuitry
- Flexible control and configuration of I/O ports
- LVCMOS compatible data and control inputs and outputs
- 75ΩECL compatible, differential, serial cable driver output
- 3.3VI/O power supply and 2.5V logic supply operation
- 64-pin TQFP package
*Patent application obtained or pending.
illustrate
The LMH0030 SMPTE 292M/259M Digital and Auxiliary Data FIFO and Integrated Cable Drive Video Serializer is a monolithic integrated circuit that encodes, serializes and transmits bit-parallel digital video data in accordance with SMPTE 125M and 267M standard definition, 10-bit wide component video and SMPTE 260M, 274M, 295M and 296M high definition, 20-bit wide component video standards. The LMH0030 operates at an SMPTE 259M serial data rate 270 Mbps , 360 Mbps SMPTE 344M serial data at a rate of 540 Mbps, and SMPTE 292M serial data at 1.485 Gbps at a rate of 1483.5. The serial data clock frequency is internally generated and requires no external frequency setting, trimming, or filtering elements.
The functions performed by the LMH0030 include: parallel to serial data conversion, data encoding for the SMPTE standard, NRZ to NRZI data format conversion, serial data clock generation and serial data, automatic detection of video rates and formats, satellite packet encoding and management insertion and serial data output drivers. The LMH0030 has automatic EDH/CRC word and logo generation and insertion circuitry per SMPTE RP-165 (standard definition) or SMPTE 292M (high definition). Optional LSB jitter is implemented to prevent pathological patterns. What makes the LMH0030 unique is its FIFO for video and auxiliary data. Video FIFO allows video data to be deferred from 0 to 4 parallel data for the purpose of timing clock cycles. Port and on-chip FIFOs and control circuitry and insert storage space auxiliary data auxiliary flags, packet and checksum auxiliary data. While the LMH0030 also has exclusive built-in self-test (BIST) and video test mode generators with SD and HD component video test modes (TPG): 4:3 and 16:9 reference black, PLL and EQ pathologicals and color bars for NTSC and PAL standard raster formats*. Color bar pattern with optional bandwidth limits in chroma and luminance conversion encoding.
The LMH0030 has a unique multi-function I/O port for direct access control and configuration settings. The port can be programmed to provide external access control capabilities and input-output metrics. Therefore, designers can customize the LMH0030 to suit the desired application. After power-up or reset commands, the LMH0030 is automatically configured to the default operating state. For output drivers, PLL and serial independent supply pins improve power supply rejection, output jitter, and noise performance.
While the LMH0030's internal circuitry is powered, +2.5 V and I/O circuitry are powered from +3.3 V. Typical power consumption is 430 mW at 1.485 Gbps including two 75Ω AC-coupled and back-end matched output loads. The device uses a 64-pin TQFP.
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- The SDTV/HDTV parallel to serial digital video interface is:
- camera
- vcr
- Telecines
- Digital video routers and switches
- Digital video processing and editing equipment
- Video test pattern generators and digital video test equipment
- Video signal generator
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