LMH0051SQE

• 5-bit LVDS interface
• No external VCO or clock requirements are required
• The clock restores serial loop pass with cable drives
• Power-down mode
• 3.3 SMBus Configuration Interface
• Small 48-pin LLP package
• Industrial temperature range: -40°C to +85°C

illustrate

The LMH0341/0041/0071/0051 SDI deserializers are part of National Semiconductor's FPGA-Connected SER/DES product family of 5-bit LVDS interfaces with FPGAs. When paired with the host's FPGA LMH0341 the input data rate is automatically detected as any of the following standards and decoded original 5-bit data word standards: DVB - ASI, SMPTE 259M, SMPTE 292M, or SMPTE 424M. see For details, the standard is per-device support.

The LMH0341 between the host FPGA interface includes a 5-bit wide LVDS bus, LVDS clock, and an SMBus interface. No need for an external VCO or clock is required. The LMH0341 of CDR detects the frequency of the input data from the stream, generating a clean clock and send clock and data from the FPGA to the host. While LMH0341, LMH0041 and LMH0071 include an integrated SMPTE standard cable driver with serial clock recovery loop-through. Please refer to Table 1 for a complete list of single-channel deserializers available in this home.

FPGA connectivity supports the SER/DES family of products, an IP kit that allows design engineers to quickly develop SER/DES products for video applications. It is packaged in a small 48-pin LLP package.

Key specifications:

• Outputs are compatible with SMPTE 259M-C, SMPTE 292M, SMPTE 424M, and DVB-ASI (see Table 1)
• Typical Power Consumption: 590 mW (Loop Pass Disability, 3G Data Rate)
• 0.6 UI minimum input jitter tolerance

apply

• The SDI interface is:
• camera
• vcr
• Video switcher
• Video editing system