peculiarity
LVDS interface host FPGA
No external VCO or clock reference is required
Integrated variable output cable drive
3.3V SMBus configuration interface
Integrated TXCLK PLL eliminates clock noise
Small 48PIN LLP package
Industrial temperature range: -40°C to 85°C
illustrate
LMH0340/0040/0070/0050 SDI Serial State FPGA Connectivity SER/DES supports 5-bit LVDS interface with FPGAs as part of the product family. The FPGA host will provide IP data formats that comply with the requirements of the DVB-ASI, SMPTE 259M-C, SMPTE 292M and SMPTE 424M standards with the output of the LMH0340. See Standard for details is per-device support.
It consists of a 5-bit wide LVDS data bus, an LVDS clock and SMBus interface between SER (Serial) and FPGA. The equipment of the LMH0340/0040/0070 SER includes an integrated cable driver, which is fully compliant with all SMPTE specifications listed above. LMH0050 has a CML output that can drive a driver for a differential transmission line or interface cable driver.
The FPGA's connectivity to the SER/DES series supports IP kits, allowing design engineers to use SER/DES products to quickly develop video applications. The SER is housed in a small 48-pin LLP package.
Key specifications:
Compliant with SMPTE 424M, SMPTE 292M, SMPTE 259M-C, and DVB-ASI outputs (see Table 1)
Typical power consumption: 440 milliwatts
30 ps typical output jitter (HD, 3G)
The application SDI interface is:
camera
DVR
Video switcher
Video editing system