LMK01000ISQE

• 30 FS additive jitter (100 Hz to 20 MHz)
• Dual clock inputs
• Programmable output channels (0 to 1600 MHz)
• External synchronization
• A pin-compatible family of timing devices
• 3.15 to 3.45 V operation
• Package: 48-pin LLP (7.0 × 7.0 × 0.8mm)

illustrate

The LMK01000 family provides an easy way to divide and distribute high-performance clock signals throughout the system. These devices provide the best noise performance and pin-to-pin compatibility with the LMK03000/LMK02000 family's high-precision clock trimming and footprint.

The LMK01000 family features two programmable clock inputs (CLKin0 and CLKIN1) that allow users to dynamically switch between different clock domains.

Each device has eight independently programmable dividers and delay-trimmed clock outputs. The output of the device can be easily synchronized (SYNC) by an external pin.