LMK03000DISQ

• The integrated VCO phase noise is very low floor
• The integrated integer N PLL has a noise contribution of 224 dBc/Hz at the prominent normalization stage
• 2 to 8 (all points) VCO divider values
• 1 channel crossover value, 2 510 (even in minutes)
• LVDS and LVPECL clock outputs
• Partially integrated loop filter
• Dedicated crossovers and delay blocks are output at each clock
• Pin-compatible clock device family
• 3.15 to 3.45 V operation
• Package: 48-pin LLP (7.0 × 7.0 × 0.8 mm)
• The performance of the 200 FS RMS clock generator (10 Hz to 20 MHz) is clocked with a clean input

illustrate

While the LMK03000 series combines high-precision clock adjustment, jitter function cleaning/refurbishment, multiplication and a reference clock assignment. The device integrates a voltage-controlled oscillator (VCO), a high-performance integer N-phase-locked loop (PLL), a partially integrated loop filter, and a combination of up to eight different LVDS and LVPECL outputs.

The output of the VCO is a port access with a selective FOUT. Internally, the various clock distribution modules output from the VCO to the feed are passed through the VCO crossover.

Each clock distribution module includes a programmable crossover, phase synchronization circuitry, programmable delay, clock output multiplexer, and an LVDS or LVPECL output buffer. This allows multiple integer-related and phase-tuned reference copies to be distributed across eight system compositions.

The clock regulator comes in a 48-pin LLP package with a footprint that is compatible with other clocks on the same home device.