LMK03001CISQ

• The integrated VCO has very low phase noise floor
• The integrated integer-N PLL has a prominent normalization stage - 224 dBc/Hz noise contribution
• 2 to 8 (all points) VCO divider values
• 1 channel divider value, 2 510 (even minutes)
• LVDS and LVPECL clock outputs
• Partially integrated loop filter
• Dedicated dividers and delay blocks are output at each clock
• A family of pin-compatible timing devices
• 3.15 to 3.45 V operation
• Package: 48-pin LLP (7.0 × 7.0 × 0.8mm)
• The performance of the 200 FS RMS clock generator (10 Hz to 20 MHz) with a clean input clock

illustrate

While the LMK03000 series combines high-precision clock adjustment, jitter functions for cleaning/refurbishment, multiplication and a reference clock assignment. The device integrates a voltage-controlled oscillator (VCO), a high-performance integer-N phase-locked loop (PLL), a partially integrated loop filter, and combinations of up to eight different LVDS and LVPECL outputs.

The output of the VCO is port access with selective FOUT. Internally, the VCO outputs to various clock distribution modules in the feed through the VCO divider.

Each clock distribution block includes a programmable divider, phase synchronization circuitry, programmable delay, clock output multiplexer, and an LVDS or LVPECL output buffer. This allows multiple reference copies of integer correlation and phase adjustment to be distributed to eight system compositions.

The clock regulator comes in a 48-pin LLP package and occupies a footprint compatible with other clocks in the same home device.