- Cascading PLLatinum PLL architecture
- PLL1
- Detection rates of up to 40 MHz
- Integrated low-noise crystal oscillator circuitry
- Dual redundant reference clock inputs with LOS
- PLL2
- Noise substrate to [1 Hz] PLL at -224 dBc/Hz
- Phase detection rates up to 100 MHz
- Input frequency multiplied
- Integrated low-noise VCO
- Ultra-low RMS jitter performance
- 150 FS RMS jitter (12 kHz - 20 MHz)
- 200 FS RMS jitter (100 Hz - 20 MHz)
- LVPECL/2VPECL, LVDS, and LVCMOS outputs
- Supports clock frequencies up to 1080 MHz
- The default clock output power (CLKout2) is the most
- Five dedicated channel dividers and delay blocks
- Pin-compatible clock device family
- Industrial grade temperature range: -40 to 85°C
- 3.15 V to 3.45 V operation
- Package: 48-pin LLP (7.0 × 7.0 × 0.8 mm)
illustrate
The LMK04000 series of high-precision clock adjustments provides low-noise jitter cleaning, clock multipliing, and distribution without the need for high-performance voltage-controlled crystal oscillators (VCXO) modules. Using a cascaded PLLatinum architecture combined with external crystals and variable displacement diodes, LMK04000 series offers root mean square (RMS) jitter performance in 200 femtoseconds (fs).
The cascade consists of two high-performance phase-locked loops (PLLs), low-noise crystal oscillator circuitry, and high-performance voltage-controlled oscillators (VCOs). The first PLL (PLL1) provides the function of a low-noise jitter eliminator, while the second PLL (PLL2) performs clock generation. The PLL1 can be configured either with an external VCXO module or with an integrated crystal oscillator using an external crystal and varactor diode. When the loop bandwidth is very narrow, the PLL1 uses a VCXO module with upper phase noise or a close approach to the crystal clean input clock (less than 50 kHz offset). The output of PLL1 is used as an input reference PLL2 clean place locked integrated VCO. The loop bandwidth of the PLL2 can be optimized to clean away phase noise (offset above 50 kHz) such as the integrated VCO over the VCXO module or the crystal PLL1.
The LMK04000 series uses dual redundant inputs, five differential outputs, and an optional default clock after power-up. The input block is equipped with signal loss detection and automatic or manual reference clock selection. Each clock output contains a programmable crossover, phase synchronization circuitry, programmable delay, and LVDS, LVPECL, LVCMOS, or output buffers. CLKout2 is available on the default startup clock, which can be used to provide a field-programmable gate array (FPGA) or the initial clock jitter clearer for microcontrollers in sequential system power schemes
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