- Cascaded PLLatinum PLL architecture
- PLL1
- Detection rates of up to 40 MHz can be achieved
- Integrated low noise crystal oscillator circuit
- Dual redundant reference clock inputs with LOS
- PLL2
- -224 dBc/Hz noise floor for the [1 Hz] PLL
- Phase detection rates up to 100 MHz
- The input frequency is multiplied
- Integrated low noise VCO
- Ultra-low RMS jitter performance
- 150 FS RMS jitter (12 kHz - 20 MHz)
- 200 FS RMS jitter (100 Hz - 20 MHz)
- LVPECL/2VPECL, LVDS and LVCMOS outputs
- Supports clock frequencies up to 1080 MHz
- The default clock output power (CLKout2) is maximum
- Five dedicated channel dividers and delay blocks
- A family of pin-compatible timing devices
- Industrial temperature range: -40 to 85 °C
- 3.15 V to 3.45 V operation
- Package: 48-pin LLP (7.0 × 7.0 × 0.8mm)
illustrate
The LMK04000 series of high-precision clock trimming provides low-noise jitter cleaning, clock multiplication and distribution without the need for high-performance voltage-controlled crystal oscillator (VCXO) modules. Using a cascaded PLLatinum architecture combined with an external crystal and varactor diode, the LMK04000 series provides root-mean-square (RMS) jitter performance in minutes of 200 femtoseconds (fs).
The cascade consists of two high-performance phase-locked loops (PLLs), a low-noise crystal oscillator circuit, and a high-performance voltage-controlled oscillator (VCO). The first PLL (PLL1) provides the function of a low noise jitter cleaner, while the second PLL (PLL2) performs clock generation. The PLL1 can be configured either with an external VCXO module or with an integrated crystal oscillator using an external crystal and varactor diode. When the loop bandwidth is narrow, PLL1 uses the upper stage phase noise VCXO block or crystal to clean the proximity of the input clock (below 50 kHz offset). The output of PLL1 serves as an input reference, and PLL2 is cleanly locked with integrated VCO. The loop bandwidth of PLL2 can be optimized for clean phase noise (offset above 50 kHz) as integrated VCO is superior to VCXO modules or crystal PLL1 use.
The LMK04000 series features dual redundant inputs, five differential outputs, and an optional default clock after power-up. The input block is equipped with loss-of-signal detection and automatic or manual reference clock selection. Each clock output contains a programmable divider, phase synchronization circuitry, programmable delay, and LVDS, LVPECL, LVCMOS, or output buffers. 默认启动时钟上CLKout2可用，它可以被用来提供一个现场可编程门阵列（FPGA）或在顺序系统电源方案的微控制器，时钟抖动清除器的初始
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