LMK04803BISQE

• Ultra-low RMS jitter performance
• 111 FS RMS jitter (12 kHz to 20 MHz)
• 123 FS RMS jitter (100 Hz to 20 MHz)
• Dual-loop PLLatinum PLL architecture
• PLL1
• Integrated low-noise crystal oscillator circuitry
• Hold mode when the input clock is lost
• Automatic or manual triggering/recovery
• PLL2
• Noise substrate to [1 Hz] PLL at -227 dBc/Hz
• The phase detection rate is up to 155 MHz
• OSCIN frequency is doubled
• Integrated low-noise VCO
• 2 LOS redundant input clock
• Automatic and manual switching modes
• 50% duty cycle output points, 1 to 1045 (odd and even)
• LVPECL, LVDS, or LVCMOS programmable outputs
• Precision digital delay, fixed or dynamically adjustable
• 25 PS one-step analog delay control.
• 14 Differential output. Up to 26 single-ended.
• Up to 6 VCXOs/crystal buffer outputs
• Up to 1536 MHz clock rate
• 0 delay mode
• The output power is up to three default clocks
• Multi-mode: dual PLL, single PLL and clock distribution
• Industrial grade temperature range: -40 to 85°C
• 3.15 V to 3.45 V operation
• Package: 64-pin LLP (9.0 × 9.0 × 0.8 mm)

illustrate

The LMK04800 series is the industry's highest performance superior clock jitter clearing, power generation, and advanced features to meet the requirements of next-generation systems to assign clock tuning. The dual-cycle PLLatinum architecture enables low-cost external crystals and variable diodes for 111 FS RMS jitter (12 kHz to 20 MHz) using low-noise VCXO modules or 200 FS RMS jitter (12 kHz to 20 MHz).

The dual-cycle structure consists of two high-performance phase-locked loops (PLLs), low-noise crystal oscillator circuitry, and high-performance voltage-controlled oscillators (VCOs). The first PLL (PLL1) provides the function of a low-noise jitter eliminator, while the second PLL (PLL2) performs clock generation. The PLL1 can be configured with either an external VCXO module or an integrated crystal oscillator with an external tunable crystal and variable capacitance diode. When the loop bandwidth is very narrow, the PLL1 uses a VCXO module with upper phase noise or a tunable crystal to clean the approach of the input clock (less than 50 kHz offset). The output of PLL1 is used as an input reference PLL2 clean place locked integrated VCO. The loop bandwidth of the PLL2 can be optimized to clean away phase noise (offset above 50 kHz) such as the integrated VCO module or the tuning crystal PLL1 that is better than the VCXO