LP2995LQX

• Low output voltage offset
• Works with +5 V, +3.3 V and 2.5 V rails
• Supply and sink current
• Low external component count
• No external resistors are required
• Linear topology
• In SO-8, it is available in a PSOP-8 or LLP-16 package
• Low cost and easy to use

illustrate

The LP2995 linear regulator is designed to meet the JEDEC SSTL-2 and terminated DDR-SDRAM SSTL-3 specifications. The device contains a high speed operational amplifier to provide excellent load transient response. The output stage prevents applications that simultaneously deliver 1.5A of continuous current and transient peak up to 3A for the termination of shooting for DDR-SDRAM. The LP2995 also features V_SENSEPins for superior load regulation and V_REFRefer to the output chipset and DDR memory.

Patent pending

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• DDR termination voltage
• SSTL - 2
• SSTL - 3