LP2995MRX

• Low output voltage offset
• Engineering with +5 V, +3.3 V and 2.5V rails
• Supply and intake current
• Low number of external components
• No external resistance is required
• Linear topology
• In SO-8, it is available in either PSOP-8 or LLP-16 packages
• Low cost and easy to use

illustrate

The LP2995 linear regulator is designed to meet JEDEC SSTL-2 and termination DDR-SDRAM SSTL-3 specifications. The device contains a high-speed op-amp to provide superior load transient response. The output stage prevents the termination shooting of DDR-SDRAM by providing a continuous current of 1.5A and a transient peak of up to 3A for applications in the application. The LP2995 also features V SENSE pins, which provide superior load regulation and V REF output chipset and DDR memory references.

Patent pending

apply

• DDR termination voltage
• SSTL - 2
• SSTL - 3