LP2996LQ

• Supply and sink current
• Low output voltage offset
• No external resistors are required
• Linear topology
• The ability to suspend to memory (STR).
• Low external component count
• Thermal shutdown
• In SO-8, it is available in a PSOP-8 or LLP-16 package

illustrate

The LP2996 linear regulator is designed to meet the JEDEC SSTL-2 specification for terminating DDR-SDRAM. The device contains a high speed operational amplifier to provide excellent load transient response. The output stage prevents applications that simultaneously deliver 1.5A of continuous current and transient peak up to 3A for the termination of shooting for DDR-SDRAM. The LP2996 also features V_SENSEPins that provide superior load regulation and one_{V REF}Output as chipset and DIMM reference.

An additional feature found in the LP2996 is an aggressive low shutdown (^SD) pin that provides the ability to suspend to memory (STR). When ^SD is pulled down V_TTOutput tri-state provides a high impedance output, however, V_REFWill remain active. Power saving advantage allows lower quiescent current in this mode.

apply

• DDR-I and DDR-II termination voltages
• SSTL-2 and SSTL-3 terminate
• HSTL termination