LP2996LQ

• Supply and intake current
• Low output voltage offset
• No external resistance is required
• Linear topology
• Functions of Suspension to Memory (STR).
• Low number of external components
• Thermal shutdown
• In SO-8, it is available in either PSOP-8 or LLP-16 packages

illustrate

The LP2996 linear regulator is designed to meet the JEDEC SSTL-2 specification for termination DDR-SDRAM. The device contains a high-speed op-amp to provide superior load transient response. The output stage prevents the termination shooting of DDR-SDRAM by providing a continuous current of 1.5A and a transient peak of up to 3A for applications in the application. The LP2996 also features a V SENSE pin that provides superior load regulation and a V REF output as a chipset and DIMM reference.

An additional feature of the LP2996 is found to be an aggressive low shutdown (^SD) pin that provides suspend to memory (STR) functionality. When ^ SD is pulled down the V TT output tristate provides a high impedance output, however, V REF will remain active. Power saving advantage in this mode through lower quiescent current.

apply

• DDR-I and DDR-II termination voltages
• SSTL-2 and SSTL-3 terminated
• HSTL terminated