LP2996M

• Source and sink current
• Low output voltage offset
• No external resistors are required
• Linear topology
• Suspend to memory (STR) function
• Low external component count
• Thermal shutdown
• Available in SO-8, PSOP-8 or LLP-16 packages

illustrate

The LP2996 linear regulator is designed to meet the JEDEC termination SSTL-2 specification for DDR-SDRAM. The device contains a high speed op amp to provide excellent load transient response. The output stage prevents applications that simultaneously deliver 1.5A of continuous current and transient peaks up to 3A for applications where DDR-SDRAM terminates the shots needed. The LP2996 also uses V_SENSEPin to provide superior load regulation and serves as a chipset and DIMM reference V_REFOutput.

Another feature found on the LP2996 is an aggressive low shutdown (^SD) pin that provides the ability to suspend to memory (STR). When ^ SD is pulled low V_TTOutput tristates provide a high impedance output, however, V_REFWill remain active. An energy-saving advantage is available in this mode through lower quiescent current.

apply

• DDR-I and DDR-II terminal voltages
• SSTL-2 and SSTL-3 terminate
• HSTL termination