LP2996MR

• source and absorb current
• Low output voltage offset
• No external resistance is required
• Linear topology
• Suspended to memory (STR) function
• Low number of external components
• Thermal shutdown
• Available in SO-8, PSOP-8 or LLP-16 packages

illustrate

The LP2996 linear regulator is designed to meet the JEDEC termination SSTL-2 specification for DDR-SDRAM. The device includes a high-speed op-amp to provide excellent load transient response. The output stage prevents DDR - SDRAM termination from being shot by simultaneously delivering 1.5A continuous current and transient peak up to 3A for applications. The LP2996 also features a V SENSE pin that provides superior load regulation and serves as a chipset and DIMM reference V REF output.

Another feature on the LP2996 is found to be a positive low shutdown (^ SD) pin that provides suspend to memory (STR) functionality. When ^ SD is pulled down the V TT output tristate provides a high impedance output, however, V REF will remain active. An energy-saving advantage is achieved in this mode through lower quiescent currents.

apply

• DDR-I and DDR-II termination voltages
• SSTL-2 and SSTL-3 terminated
• HSTL terminated