LPC4074FBD144,551
The LPC407x is an ARM Cortex-M4-based digital signal controller for embedded applications requiring high integration and low power consumption.
The ARM Cortex-M4 is a next-generation core that offers system-enhanced features such as low power consumption, enhanced debug features and a high level of block integration support. The ARM Cortex-M4 CPU consists of a 3-stage pipeline with Harvard architecture with a separate local instruction and data bus, a third bus for peripherals, and an internal prefetch unit including support for speculative branching, the ARM Cortex-M4 supports a single-cycle digital signal processor and SIMD instructions. Several versions of this model have a hardware floating-point processor integrated into the core.
The LPC407x adds a dedicated flash accelerator for optimal performance when encoding from flash. The LPC407x is designed to run at CPU frequencies up to 120 MHz.
The LPC408x's rich peripherals include up to 512 kB of flash program memory, up to 96 kB of SRAM data memory, up to 4032 bytes of EEPROM data memory, external memory controller (EMC), LCD, Ethernet, USB device/host/OTG, 1 SPI flash interface, 1 general-purpose DMA controller, 5 UART, 3 SSP controllers, 3 I2C-bus interfaces, 1 quadrature encoder interface, 4 general-purpose timers, 2 general-purpose PWMs (6 outputs each) and 1 motor control PWM, 1 ultra-low power RTC with split battery power and event recorder, 1 windowed watchdog timer, 1 CRC calculation engine, and up to 165 general-purpose I/O pins.
Analog peripherals include an 8-channel 12-bit ADC, two analog comparators, and a DAC.
The LPC407x pins are designed to be pin-functionally compatible with the LPC24xx/23xx and LPC178x/7x families.
Features and benefits
- Functional replacements for the LPC23xx/24xx and LPC178x/7x family of devices.
- ARM's Cortex-M4 core:
- ARM Cortex-M4 processor operating at up to 120 MHz.
- The ARM Cortex-M4 has a built-in memory protection unit (MPU) supporting 8 zones.
- The ARM Cortex-M4 has a built-in nestable vector interrupt controller (NVIC).
- Hardware floating-point unit (not all versions).
- Unmasked interrupt (NMI) input.
- JTAG and serial debugging (SWD), serial tracing, 8 breakpoints, and 4 watchpoints.
- System beat timer.
- System:
- The multilayer AHB matrix interconnect provides a separate bus for each AHB host. The AHB host includes a CPU and a general-purpose DMA controller. This interconnect provides communication without quorum delay unless two masters attempt to access the same slave at the same time.
- The split APB bus enables fewer stalls between the CPU and DMA, resulting in higher throughput. A single-level write buffer allows the CPU to continue running without waiting for APB writes to complete when APB is not busy.
- Embedded trace macrocell (ETM) module with real-time tracking.
- Boundary scan to simplify board testing.
- Memorizer:
- 128 KB of on-chip flash program memory for in-system programming (ISP) and in-application programming (IAP) capabilities that combine enhanced Flash memory accelerators with Flash memory locations on the CPU's local code/data bus to deliver high code performance through flash.
- Up to 96 kB of on-chip SRAM includes: 64 kB main SRAM on the CPU for high-performance access to the CPU via local code/data bus. Two 16 kB peripheral SRAM modules with independent access paths for higher throughput. These SRAM modules can be used for DMA memory as well as general purpose instruction and data storage.
- Up to 4032 bytes of on-chip EEPROM.
- External memory controllers (EMC) support asynchronous static memory devices such as RAM, ROM, flash memory, and dynamic storage such as single data rate SDRAM.
- The 8-channel General Purpose DMA Controller (GPDMA) on the AHB multilayer matrix can be used for SSP, I2S, UART, CRC engine, analog-to-digital and digital-to-analog converter peripherals, timer matching signals, GPIOs, and memory-to-memory transfer.
- Serial interface:
- Quad SPI Flash Interface (SPIFI) with four lanes and up to 40 MB/s.
- Ethernet MAC with MII/RMII interface and associated DMA controller. These functions are housed in a separate AHB.
- USB 2.0 full-speed dual-port device/host/OTG controller with on-chip PHY and associated DMA controller.
- 5 UART with decimal baud rate generator, internal FIFO, DMA support and RS-485/EIA-485 support. One UART (UART1) has full modem control I/O, while one UART (USART4) supports IrDA, synchronous mode, and ISO7816-3 compliant smart card mode.
- 3 SSP controllers with FIFO and multi-protocol capabilities. The SSP interface is available for GPDMA controllers.
- Three enhanced I²C-bus interfaces, one with true open-drain output (supporting full I²C-bus specification and ultra-fast mode with a data rate of 1 Mbit/s), and two standard port pins. Enhancements include multi-address identification and monitoring modes.
- I²S (Inter-IC Sound) interface for digital audio input or output. Can be used for GPDMA.
- Dual channel CAN controller.
- Digital peripherals:
- SD/MMC memory card interface.
- Up to 165 general-purpose input/output (GPIO) pins with configurable pull-up/pull-down resistors, open-drain mode, and transponder modes, depending on package format. All GPIOs are located on the AHB bus for fast access and support for Cortex-M4 bit-segment technology. GPIOs can be accessed through a universal DMA controller. Any pin on ports 0 and 2 can be used to generate an interrupt.
- Two external interrupt inputs configurable for edge/level triggering. All pins on port 0 and port 2 can be used as edge-triggered interrupt sources.
- 4 general-purpose timers/counters with a total of 8 capture inputs and 10 matched outputs. Each timer block has an external counter input. Specific timer events can be selected to generate DMA requests.
- Quadrature encoder interface to monitor an external quadrature encoder.
- Two standard PWM/timer modules with external counter input options.
- One motor control PWM for three-phase motor control.
- Real-time clock (RTC) with independent power domain. The RTC is timed by a dedicated RTC oscillator. The RTC block includes a 20-byte battery-powered backup register that allows the system state to be stored if the rest of the chip is powered down. Battery power can be provided from a standard 3 V lithium coin cell battery. When the battery voltage drops to 2.1 V, the RTC continues to operate. RTC interrupts wake the CPU from any low-power mode.
- The event logger captures the clock value when an event occurs in any of the three inputs. Event identification and its occurrence time are stored in registers. The event logger is located in the RTC power domain, so it can operate as long as the RTC power supply is present.
- Windowed Watchdog Timer (WWDT). Windowed operation, dedicated internal oscillator, watchdog warning interrupt and safety functions.
- The CRC engine block calculates CRC from the provided data using one of three standard polynomials. The CRC engine can be used with DMA controllers to generate CRC without the need for the CPU to participate in data transfer.
- Analog peripherals:
- A 12-bit analog-to-digital converter (ADC) that multiplexes input in 8 pins at conversion rates up to 400 kHz with multiple result registers. A 12-bit ADC can be used with a GPDMA controller.
- 10-bit digital-to-analog converter (DAC) with dedicated conversion timer and DMA support.
- 2 analog comparators.
- Power Control:
- 4 low-power modes: Sleep Mode, Deep Sleep Mode, Power-Down Mode, and Deep Power-Down Mode.
- The Wake-Up Interrupt Controller (WIC) allows the CPU to automatically wake up any priority interrupt when the clock stops in deep sleep mode, power-down mode, and deep power-down mode.
- The processor wakes up from power-down mode via any interrupt that can run in power-down mode, including external interrupts, RTC interrupts, PORT0/2 pin interrupts, and NMI.
- Power-down detection with independent thresholds for interrupt and forced reset.
- On-chip power-on reset (POR).
- Clock generation:
- The clock output function reflects the main oscillator clock, IRC clock, RTC clock, CPU clock, USB clock, or watchdog timer clock.
- On-chip crystal oscillator operating from 1 MHz to 25 MHz.
- An internal 12 MHz RC oscillator (IRC) calibrates accuracy to 1 % for optional use as a system clock.
- An on-chip PLL allows the CPU to run at maximum CPU rate without the need for a high-frequency crystal. Can be operated from the main oscillator or the internal RC oscillator.
- A second dedicated PLL can be used for the USB interface to increase the flexibility of the main PLL setup.
- The universal pin function selection feature provides many possibilities for using on-chip peripheral functions.
- A unique serial number that can be used as a chip identification.
- Single 3.3 V supply (2.4 V to 3.6 V). Temperature range: -40 ºC to +85 ºC
- Available in LQFP208, TFBGA208, TFBGA180, LQFP144 and LQFP80 packages.
apply
- Correspondence:
- POS terminals, network servers, multi-protocol bridges
- Industrial/Medical:
- Automation controllers, application control, robot control, HVAC, PLC, inverters, circuit breakers, medical scanning, security monitoring, motor drives, video calls
- Consumer Goods/Home Appliances:
- Audio, MP3 decoder, alarm system, monitor, printer, scanner, small household appliance, fitness equipment
- Car: