MC9S12NE64VTUE

• Product introduction

MC9S12NE64VTUE microcontroller

characteristic

• 16-bit HCS12 core
  • HCS12 CPU
  • Compatible with instruction sets above M68HC11
  • The interrupt stack and programmer model are the same as the M68HC11
  • Instruction queue
  • Enhanced variable addressing
  • Memory Mapping and Interface (MMC)
  • Interrupt Control (INT)
  • Background Debugging Mode (BDM)
  • Enhanced debug12 module, including breakpoints and traffic change tracking buffers (DBGs)
  • Multiplexing Extended Bus Interface (MEBI) – Available in 112-pin packages only
• Wake-up interrupt input
  • The 21 port bits can be configured for wake-up interrupts with digital filtering
• memory
  • 64K bytes of flash EEPROM
  • 8K bytes of RAM
• Analog-to-Digital Converters (ATDs)
• Serial interface
  • Two Asynchronous Serial Communication Interfaces (SCI)
  • One synchronous serial peripheral interface (SPI)
  • Built-in IC bus (IIC)
• Ethernet Media Access Controller (EMAC)
  • IEEE 802.3 compatible
  • Standalone Media Interface (MII)
  • Full-duplex and half-duplex modes
  • Use the pause box to control the process
  • MII management features
  • Address identification
  • Frames with broadcast addresses are always accepted or rejected
  • Exact match of individual 48-bit single (unicast) addresses
  • Hash (64-bit hash function) check for swarm (multicast) addresses
  • Promiscuous mode
• Ethernet type filter
• Loopback mode
• Two receive and one transport Ethernet buffer interface
• Ethernet 10/100 Mbps transceiver (EPHY)
• Available in 80-pin TQFP-EP or 112-pin LQFP packages