MSC8144AMC-SAQuad-coreDSP
MSC8144processorIt is the third generation of Freescale's high-performance multicore DSP devices, wired and wireless infrastructure applications.It is built on the successful previous multi-core DSP design to enhance the rapidly expanding voice/video/data triple playback services in this area.This multi-core DSP offers the industry's highest level of performance and integration, combined with four fully programmable StarCore DSP cores, each running at up to 1 GHz in a highly optimized architecture for voice, fax, video, and data compression processing.
The packet processor inside the QUICC engine of dual RISC supports multiple network protocols to ensure reliable data transmission over the packet network, while significantly offloading such processing to the DSP core.
The MSC8144 embeds the industry's largest internal memory and supports a variety of advanced interface types, including high-speed Ethernet and UTOPIA network communications, DDR controller high-speed, industry-standard memory interfaces, and multi-channel TDM interfaces for connecting toPSTN networking and serial RapidIO® and PCI interfaces are used to connect to other devices mounted in the same rack or board.
As a highly flexible, fully programmable, and powerful multimedia DSP, the MSC8144 delivers powerful processing power while maintaining a competitive price and power consumption per channel.
peculiarity
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4 x 800 MHz/1 GHz StarCore SC3400 DSP extended core
16 ALUs provide up to 12,008 MMACS
Performance is equivalent to a 3.2/4.0 GHz SC3400 core
Each expansion core has a DSP core processor and dedicated instruction cache, data cache, memory management unit (MMU), interrupt controller (EPIC), and timer
The industry's largest on-chip memory
Four 16 KB L1 instruction caches (per core)
Four 32 KB L1 data caches (per core)
A 128 KB shared L2 instruction cache
A 512 KB shared M2 stores critical data and temporary data buffering
10 MB of 128-bit wide shared M3 memory, no external memory required for most applications
96 KB boot ROM bootable from four cores, I²C serial RapidIO, PCI and Ethernet interfaces, through support boot.
DDR memory controller clocked at up to 200 MHz (400 MHz data rate) DDR SDRAM, 32-bit data bus with 64 MB to 4 GB DDR and DDR2 devices with x8/x16 data ports (no direct x4 support),Configuration 1 GB including two physical banks (chip select), each independently addressed, double-bit error detection and single-bit error correction (ECC)
The internal DMA controller has 16 bidirectional time-sharing multiplexed channels that enable data transfer between the internal memory and the serial interface
Eight independent time division multiplexing (TDM) interfaces with eight TDM interfaces assigned to the 2048 DS-0 (64 kbps) channel
The QUICC engine communicates the processor, configures and controls both Ethernet and ATM (UTOPIA) interfaces and offloads the communication tasks of the DSP core.It includes 2 x 32-bit RISC processors, 48 KB of multi-host multi-port RAM, 48 KB of instruction RAM, serial DMA channels, control hardware, baud rate generator, clock synthesizer, interrupt controller and three communication controllers.
Two GB Ethernet controllers supporting 10/100/1000 Mbps operation using MII, RMII, SMII, RGMII and SGMII physical interfaces
ATM controller that supports UTOPIA interface and AAL0, AAL2 and AAL5 operation
The serial RapidIO port supports 1x/4x running message units
The PCI interface is designed to conform to the PCI specification revision 2.2 operating system, at 33 or 66 MHz and 3.3 volts
RS-232 interface of UART
Serial Peripheral Interface (SPI)
The I²C interface starts from EEPROM
The interrupt system, including an enhanced programmable interrupt controller (EPIC) with up to 256 interrupts per core and 32 priorities, up to 32 virtual interrupts generates a simple write access and virtual NMI interrupt output using an external interrupt output
Sixteen 16-bit programmable timers, two 32-bit general-purpose timers per core in four quad timer modules, and four software watchdog timer modules
32 GPIOs, 16 of which can be configured as externally maskable interrupts (IRQs)
8 programmable hardware signal lights
Debugging capabilities through the JTAG interface and OCE30's modules, debugging and profiling capabilities in most device modules
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