MSC8144VT800A Quad-core DSP
MSC8144 processor is the third generation of Freescale's high-performance multi-core DSP devices, targeted at wired and wireless infrastructure applications. It is built on the design of the successful multi-core DSP to enhance the rapidly expanding voice/video/data triple playback service in this field. This multi-core DSP offers the industry's highest level of performance and integration, combined with four fully programmable StarCore DSP cores, each running on a highly optimized architecture for voice, fax, video, and data compression processing at speeds up to 1 GHz. The packet processor inside the QUICC engine of dual RISC supports multiple network protocols to ensure reliable data transmission over the packet network while significantly offloading DSP cores for such processing. The MSC8144 embeds the industry's largest internal memory and supports a variety of advanced interface types, including high-speed Ethernet and UTOPIA network communications, DDR controller high-speed, industry-standard memory interfaces, multi-channel TDM interfaces for connecting to PSTN networks and serial RapidIO® and PCI interfaces for connecting to other devices mounted on the same rack or board. As a highly flexible, fully programmable, powerful multimedia DSP MSC8144 delivers powerful processing power while maintaining competitive pricing and power per channel. Features-------------------------------------------------- ------------------------------ 4 800 MHz/1 GHz StarCore SC3400 DSP Extended Core 16 ALUs provide up to 12,000 MMACS performance equivalent to a 3.2/4.0 The GHz SC3400 core has a DSP core processor and dedicated instruction cache for each expansion core, a data cache, a memory management unit (MMU), an interrupt controller (EPIC), and a timer, the industry's largest on-chip memory, four 16 KB L1 instruction caches (per core), four 32 KB L1 data caches (per core), a 128 KB shared L2 instruction cache, a 512 KB shared M2 storage for critical data, and temporary data buffers10 MB wide shared M3 memory without external memory for most applications 96 KB of boot ROM, bootable from four cores, I²C serial RapidIO, PCI and Ethernet interfaces, via support. DDR SDRAM clocked at up to 200 MHz (400 MHz data rate) for DDR memory controller, 32-bit data bus with 64 MB to 4 GB of DDR and DDR2 devices with x8/x16 data ports (no direct x4 support), 1 GB configuration including two physical banks (chip selection), each with independent addressing, dual-bit error detection and single-bit error correction (ECC) The internal DMA controller has 16 channels of bidirectional time-sharing multiplexing, Enables data transfer between internal memory and serial interfaces Eight independent time-division multiplexing (TDM) interfaces, 8 TDM interfaces with 2048 DS-0 (64 kbps) channels to allocate 8 TDM interfaces to the QUICC engine communication processor, configure and control communication tasks for the two Ethernet and ATM (UTOPIA) interfaces and offload the processing of DSP cores. It includes 2 x 32-bit RISC processors, 48 KB of multi-host multi-port RAM, 48 KB of instruction RAM, serial DMA channels, control hardware, baud rate generator, clock synthesizer, interrupt controller and three communication controllers. Two GB Ethernet controllers supporting 10/100/1000 Mbps operation ATM controllers with MII, RMII, SMII, RGMII and SGMII physical interfaces, serial RapidIO ports supporting UTOPIA interfaces and AAL0, AAL2 and AAL5 operation Message units running 1x/4x PCI interface design, compliant with PCI specification Revision 2.2 operating system, in 33 or 66 The RS-232 interface with MHz and 3.3 volt UART, the Serial Peripheral Interface (SPI), and the I²C interface initiate the interrupt system from the EEPROM, including an enhanced Programmable Interrupt Controller (EPIC) for up to 256 interrupts per core and 32 priorities, a simple write access generated by up to 32 virtual interrupts and a virtual NMI interrupt centralized using external interrupts to output 16 16-bit programmable timers, in four quad timer modules, two 32-bit universal timers per core, and four software watchdog timer modules with 32 GPIOs 16 of them can be configured as external shieldable interrupts (IRQ) 8 programmable hardware signal light debugging capabilities via JTAG interface and OCE30 modules, debugging and analysis capabilities in most device modules
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