MSC8154ETVT1000BHigh-performance fournucleusDSP
The MSC8154 device is Freescale's fourth generation of high-end multicore DSP devices targeting broadband wireless base stations and other communications infrastructures.The quad-core DSP MSC8154 is based on Freescale's SC3850 StarCore technology and is designed to advance the capabilities of wireless broadband devices.It offers industry-leading performance and power consumption, leveraging 45nm process technology to deliver a highly integrated system-on-chip (SoC) with performance equivalent to a 4 GHz single-core device.The MSC8154 helps device manufacturers and operators create solutions and services that will make it mainstream in the near term, next-generation wireless standards such as 3G-LTE, WiMAX and HSPA+ and TDD-LTE.The device is designed to reduce system cost by integrating features into a single device that previously required multiple discrete components.
The MSC8154 DSP offers a high level of performance and integration, combined with a new and enhanced architecture of four fully programmable SC3850 DSP cores running at speeds up to 1 GHz for wireless infrastructure applications.Developed and integrated on-chip by Freescale, the MAPLE-B baseband accelerometer supports hardware-accelerated Turbo and Viterbi channel decoding and DFT/IDFT and FFT/IFFT algorithms, and includes CRC processing.The internal RISC-based QUICC Engine subsystem supports multiple network protocols to guarantee reliable data transmission over packet networks while significantly offloading the processing of DSP cores
The MSC8154 has built-in high-capacity memory and supports a variety of advanced, high-speed interface types, including two RapidIO® interfaces, two Gigabit Ethernet interfaces for network communications, a PCI Express® controller, and a DDR controller for high-speed, industry-standard memoryinterface and four multichannel time division multiplexing (TDM) interfaces.The MSC8154 is pin-compatible with the MSC8156.
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The four StarCore SC3850 DSP core subsystems operate at frequencies up to 1 GHz/8000 MMACS per core and up to 32000 MMACS per device.
Multi-baseband accelerator platform engine (MAPLE-B)
High-speed, high-bandwidth fabric-like arbitration between DSP cores and other best-in-class master memory, M2 M3 memory, DDR controller, MAPLE-B and configuration registers
Two DDR controllers with up to 400 MHz clock (800 MHz data) rates and 32/64-bit DDR2/3 SDRAM data bus
32-channel DMA controller
The dual-RISC core QUICC Engine subsystem runs at up to 500 MHz
HSSI, supporting two 4x SerDes ports
Quad TDM interface
UART, I²C interface
8 software watchdog timers
Sixteen 16-bit timers and two 32-bit general-purpose timers with per-core RTOS support.
I/O interrupt centralized and virtual interrupt support, 8 hardware semaphore lights
36 GPIO ports multiplex interface signals and IRQ inputs
Boot options: Ethernet, Serial RapidIO, I²C Serial Peripheral Interface (SPI)
Three input clocks and phase-locked loops
The JTAG test access port (TAP) and boundary scan architecture are designed to comply with IEEE® standards.1149.1™ Analysis and performance monitoring support
Low-power standby mode reduces power consumption by waiting, stopping and power dropping
Optimized power management circuitry
CMOS 45nm SOI technology is available in a 29mm x 29mm, 783-ball FC-PBGA package
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