MSC8157ADSMSC8157 DSPBroadband wireless access
The MSC8157 targets high-bandwidth computing DSP applications and optimized 3G-LTE (FDD and TDD), UMTS and WiMAX systems.The device includes a fully programmable DSP core and powerful hardware acceleration that delivers best-in-class performance, power efficiency, connectivity, and cost-effectiveness.
peculiarity
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Core frequencies up to 48000 MMACS 600 SC3850 cores operate at 1 GHz.The core subsystem supports several large zones, memory/cache, memory controller, and interrupt controller
Best-in-class high-speed non-blocking interconnect architecture to provide optimal throughput between all internal device blocks
The MAPLE-B2 supports Turbo decoding rate matching, supporting up to 330 MB/s for 3GLTE, up to 300 MB/s for WiMAX in UMTS and up to 260 Mbps for Turbo-encoded information at octave iteration to match the bit rate900 Mbps 3G LTE and WiMAX and UMTS up to 450 Mbps Viterbi decodes up to 200 Mbps K=9, zero tailing and up to 175 Mbps K=7 tailbiting, FFT/IFFT processing, supports up to 960 Msps;DFT/IDFT processing, supports up to 630 MSPS, supports CRC checksum insertion up to 10 Gbps.
DMA controller with 16 bidirectional channel pairs
Internal data analysis to optimize data throughput during development
The dual-RISC core QUICC Engine subsystem supports two SGMII/RGMII interfaces and a serial peripheral interface (SPI)
HSSI complex with OCN cloth, two 4-channel DMA controllers, two serial RapidIO ports, an enhanced messaging unit and 10 SerDes channels multiplexed two Serial RapidIO® x4/x2/x1 interfaces to five Gbaud, PCI Express®x4/x2/x1Interface, 6 CPRI channels, and two SGMIIs.
8 programmable hardware signals to manage resources
Other serial interfaces: UART, Timer, I²C, GPIO, Interrupt, and JTAG
Power: Core power 1 volt nominal, I/O power consumption, 1.0 volts, 1.5 volts and 2.5 volts nominal
Flip chip plastic ball grid array (FC-PBGA), 783 balls, 1 mm pitch, 29 mm × 29 mm.
The optional security engine (version E) provides data encryption/decryption.
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