peculiarity
Capable of running all existing 16450 software.
Pins Except for the pins CSOUT(24) and NC(29), they are compatible with the existing 16450. TXRDY##和RXRDY分别 for the former CSOUT and NC pins.
After reset, all register 16450 register sets are the same.
In FIFO mode, transmitters and receivers buffer each 16-byte FIFO to reduce the number of interrrupts submitted to the CPU.
Add or remove standard asynchronous communication bits (start, stop, and parity) or from serial data.
The Holding and Shift Register 16450 mode eliminates the need for precise synchronization and serial data between CPUs.
Independent control, transmission, reception, line status and data setting interruptions.
The programmable baud rate generator arbitrarily inputs clock 1 (2 16 - 1) and produces a 16 × clock.
Independent receiver clock input.
Modem control functions (CTS, RTS, DSR, DTR, RI and DCD).
Features of the fully programmable serial interface:
5 - , 6 - , 7 - or 8 digit characters
Generation and detection of even, odd or non-parity bits
1 - , 1 and a half - , or 2 one-stop bits
Baud rate generation (DC 1.5M baud).
False start bit detection.
Complete status reporting function.
TRI - STATE ® TTL drive data and control bus.
Generation and detection of line interruptions.
Internal fault diagnosis function:
Loopback control for fault isolation of communication links
Rest, odd-even, overflow, frame error simulation.
All priority interrupts system control.
illustrate
PC16550D is a modified version of the original 16450 Universal Asynchronous Receiver/Transmitter (UART). Functionally equivalent to powering up 16450 (character mode)* PC16550D can enter standby mode (FIFO mode) to reduce the excessive software overhead of the CPU.
In this mode, 16 bytes (plus 3 bits of RCVR FIFO error data per byte) are allowed to be stored in receive and send modes to activate the internal FIFO. All logic chips are used to minimize system overhead and maximize system efficiency. The two pin functions have been changed to allow the signal transmitted by the DMA.
UART performs serial to parallel conversion, data characters received from peripherals or modems, and parallel-to-serial data characters converted from the CPU. The CPU can read the full state of the UART at any time during the function's operation. Status information, including the type and conditions of the transfer operation being performed by the UART, as well as any error conditions (parity, overflow, frame, or interval interruption).
UART includes a programmable baud rate generator that is 1 divided by the divisor timing reference clock input (2 16 -1) and produces a 16 × clock drive internal transmitter logic. The provision also includes the use of a 16-× clock to drive the receiver logic. UART has full modem control capabilities, as well as a processor interrupt system. Interrupts can be programmed to minimize the calculation of the communication links that need to be processed at the user's request.
UART is based on the advanced M2 CMOS process of National Semiconductor Corporation.
* Can also be reset under software control, in 16450 mode.
† Note: This part of the patent.