SCAN921025HSM

• High temperature operation up to 125°C
• IEEE 1149.1 (JTAG) standard, in high-speed BIST test mode.
• The clock resumes PLL lock mode from random data.
• Ensure every data transfer cycle transition
• 芯片组（TX + RX）功耗
• Single-differential pairs eliminate multi-channel skew
• 800 Mbps Serial Bus LVDS Data Rate (at 80MHz Clock)
• 10-bit parallel interface, 1 byte of data plus 2 control bits
• Sync mode and LOCK indicator
• Triggered at the edge of the programmable clock
• Turn off the power supply when the receiver input impedance is high
• The bus LVDS serial output is rated at 27 load
• Small 49-pin BGA package

illustrate

The SCAN921025H converts into a 10-bit wide parallel LVCMOS/LVTTL data bus for LVDS serial data streams with a high-speed bus with an embedded clock. The SCAN921226H receives the bus LVDS serial data stream and converts it back to a 10-bit wide parallel data bus and restores the parallel clock.

Both devices comply with the IEEE 1149.1 standard for boundary scan testing. IEEE 1149.1 features provide design or test interconnection through a standard test access port (TAP) backplane or cable interconnect and the ability to validate differential signal integrity for use by engineers. The device pair also features a high-speed BIST mode, allowing the serializers between the interconnects to be validated at high speeds.

Data is transmitted via the backplane's SCAN921025H or cable. Single-differential pairs of data channels make PCB design easier. In addition, reducing the number of cables, PCB traces, and connector sizes greatly reduces costs. It eliminates clock-to-data and data-to-data offsets due to one output clock and data transfer serial bit. The power supply of any equipment is not used when the power supply current is reduced when the power off pin is reduced. On powered-on serial, you can choose to activate the synchronization mode or allow the deserializer to use the Sync to Random Data feature. By using synchronous mode, the deserializer will establish a signal specified during the lock lock time. In addition, the embedded clock guarantees a transition every 12-bit cycle on the bus. This eliminates the condition of charging cables due to transmission errors. In addition, you can achieve a high impedance state with the output pin SCAN921025H the three-state. The PLL can be locked to 20 MHz and 80 MHz frequencies.

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