SCAN921025HSM

• High temperature operation up to 125 °C
• IEEE 1149.1 (JTAG) standard, in high-speed BIST test mode.
• The clock recovers PLL lock mode from random data.
• Ensure every data transfer cycle transition
• Chipset (TX + RX) power consumption
• Single differential pair eliminates multichannel skew
• 800 Mbps serial bus LVDS data rate (clock at 80MHz)
• 10-bit parallel interface, 1 byte of data plus 2 control bits
• Sync mode and LOCK indicator
• Triggered at the edge of the programmable clock
• Turn off the power when the receiver input impedance is high
• The bus LVDS serial output is rated at 27 load
• Small 49-pin BGA package

illustrate

The SCAN921025H converts a 10-bit wide parallel LVCMOS/LVTTL data bus to a high-speed bus with embedded clock LVDS serial data streams. The SCAN921226H receives the LVDS serial data stream on the bus and converts it back to a 10-bit wide parallel data bus and resumes the parallel clock.

Both devices comply with the IEEE 1149.1 standard for boundary scan testing. IEEE 1149.1 features provide design or test backplane or cable interconnect through standard test access ports (TAPs) and are capable of verifying differential signal integrity for engineers to use. The device pair also has a high-speed BIST mode so that the interconnect between serializers will be verified at high speed.

Data is transmitted through the SCAN921025H or cable on the backplane. The single differential pair of data paths makes PCB design easier. In addition, reducing the number of cables, PCB traces and connector sizes greatly reduces costs. Thanks to an output clock and data transfer serial bit, it eliminates clock-to-data and data-to-data skew. The power off pin saves the power supply and does not use the power supply of any device when the current is reduced. When plugged in serial, you can choose to activate sync mode or allow the deserializer to use the Synchronize to Random Data feature. By using synchronous mode, the deserializer establishes a signal specified within the lock lock time. In addition, the embedded clock guarantees every 12-bit cycle transition on the bus. This eliminates the condition of charging the cable due to transmission errors. In addition, you can implement a high-impedance state on the three-state SCAN921025H output pin. The PLL can be locked to 20 MHz and 80 MHz frequencies.

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