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TP3054WM-X
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TP3054WM-X

  • 所属类别:转换器
  • 产品名称:扩展温度串行接口编解码器/滤波器
  • 厂商:NSC
  • 生产批号:10+11+
  • 封装:SOP16
  • 库存状态:有库存
  • 库存量:48200
  • 最低订购量:1
  • 详细资料:点击查找TP3054WM-X的pdf资料
  • 点击询价
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  • Product Introduction

peculiarity

-40°C to +85°C operation Complete codecs and filtering systems (COMBOs), including: Transmit high-pass and low-pass filtering Receive a low-pass filter for X/X correction Active RC noise filter μ or A-law compatible encoders and decoders Internal precision voltage reference Serial I/O interface Internal automatic zero circuit μ method, 16 pins - TP3054 One Law, 16 Stitches, TP3057 Designed for D3/D4 and CCITT applications ± 5V operation Low operating power is generally 50 milliwatts Power-down standby mode, usually 3 megawatts Automatic power off TTL or CMOS compatible digital interface Maximize circuit density of line interface cards Double-nemometer or PCC surface mount package See also "Design techniques for codec/filter combination circuits" AN-370,

illustrate

The TP3054, TP3057 family is illustrated by the A/D and D/A conversion architectures used by μ and A-law monolithic PCM codecs/filters, and a serial PCM interface. These devices all use the national advanced double-layer polysilicon CMOS process (microCMOS).

The coding section of each device includes an input gain adjustment amplifier, an active RC pre-filter that enters a switching capacitive bandpass filter before rejecting signals below 200 Hz and above 3400 Hz, thus eliminating noise at very high frequencies. In addition, an auto-zeroing circuit and an amplifier are included to sample and encode the filtered signal in a compandedμ or A-law PCM format. The decoding section of each device consists of an ever-expanding decoder that reconstructs the companded μ law or A-law code, corrects the response of the X/X decoder output to a low-pass filter, analog signal, and rejects signals above 3400 Hz, capable of driving low-impedance loads. The device requires two master clocks for transmission and reception of 1.536 MHz, 1.544 MHz or 2.048 MHz, which may be asynchronous, transmit and receive bit clocks, which can vary from 64 kHz to 2.048 MHz; Send and receive frame synchronization pulses. The timing of frame synchronization pulses and PCM data is compatible with both industry-standard formats.

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