- Four A/V clocks at the same time produce a phase-locked loop
- PLL1:27 or 13.5 MHz
- PLL2: 148.5 or 74.25 MHz
- PLL3: 148.5/1.001 or 74.25/1.001 MHz
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PLL4: 98.304 MHz/2 X (X = 0 to 15)
- 3 × 2 video clock intersection
- Flexible PLL bandwidth optimizes jitter performance and lock-on time
- Soft resync to the new reference
- Reference to digital deferral or loss runs freely
- For reference and PLL loss status flag
- 3.3V single supply operation
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I 2 C Interface and Address Selection Pin (3 Countries)
illustrate
LMH1983 chip is a highly integrated, programmable audio/video (A/V) clock generator designed for broadcast and professional applications. It can replace multiple PLLs and support SMPTE Serial Digital Video (SDI) and Digital Audio AES3/EBU standard application voltage control. It provides a low-jitter reference clock for any SDI transmitter to meet the strict specifications of cleaning circuits without additional clock output jitter.
LMH1983 chip features automatic input format detection, multiple A/V output formats, digital colock or free run mode, and overrides programmable simple programming of various automatic functions. Accepted input formats include HVF synchronization of major video standards, 27 MHz, 10 MHz, and 32/44.1/48/96 kHz audio word clocks.
The dual-stage PLL architecture integrates four phase-locked loops of three on-chip VCOs. The first stage (PLL1) uses a narrow loop bandwidth external low-noise 27MHz VCXO to provide a clean reference clock for the next stage. The second stage (PLL2,3,4) consists of three parallel main digital A/V clocks at the base rate, including 148.5 MHz, 148.5/1.001 MHz, and 98.304 MHz (4X 24.576 MHz) simultaneously generating VCO's PLL. Each PLL can generate clocks and timing pulses to indicate the top of the frame (TOF).
When locked as a reference, the internal 10-bit ADC will track the loop filter to control the voltage. When a reference (LOR) loss occurs, the LMH1983 chip can be programmed to save the output accuracy of the control voltage to maintain the front reference (typical) of ± 0.5 ppm. LMH1983 chip can be configured to re-sync to a pre-operation reference with few burrs.
LMH1983 chip is available in a space-saving 6 mm x 6 mm 40-pin LLP package.
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- Three-rate (3G/HD/SD) SDI deserializer
- FPGA's reference clock generation/cleaning
- Audio embedding/de-embedding
- camera
- Frame Synchronizer (Synchrolock, DARS)
- AD/DA conversion, editing, processing cards
- Keyers and flag inserters
- Format/Standard Converter
- Video display and projector
- A/V test and measurement equipment
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