- 15-66 MHz 18:1/1:18 serializer/deserializer (2.376 Gbps full-duplex throughput)
- Independent clock independent transmitter and receiver operation, enable, and down pin power
- Hot-swap protection (high-impedance power-up) and synchronization (receiver lock for random data)
- The reference clock ± 5% wide allows the system design to use locally generated clock frequency tolerances
- line and local loopback modes
- Low electromagnetic interference (EMI) for serial transmission between the Lebax BLVDS backplane and the cable
- No external coding required
- Internal PLL, no external PLL element required
- +3.3 V single power supply
- Low power consumption: 90 mA (typical) transmitter, 100mA 66 MHz PRBS-15 mode (typical)
- ± receiver input threshold of 100 mV
- Lock detection and reporting of pin losses
- Industrial -40 to +85°C temperature range
- > 2.0KV HBM ESD
- Compact, standard 80-pin LQFP package
illustrate
DS92LV18 Serial/Serializer (SERDES) pair transparently converts into an 18-bit parallel bus with embedded clock information BLVDS serial data streams. This single serial data stream simplifies the transmission of 18-bit, even fewer PCB traces and cables by eliminating bias issues between parallel data and clock paths, buses. It saves system costs and narrows the data path, which reduces the size and pins of PCB layers, cable widths, and connectors.
This SERDES has the ability to test systems and devices including built-in. The line loopback feature enables the user to check the integrity of the transmitter and receiver's serial data transmission path, while the deserialized serial data receiver outputs parallel data. Local loopback capability enables the user to check the integrity of transceivers from the local parallel bus side.
DS92LV18 adopts modified BLVDS high-speed I/O signals Reliable data transmission over the BLVDS serial transmission path provides a low-power and low-noise environment. Currents of equal magnitude and opposite directions control the edge field generated by EMI coupling via a differential data path.
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