peculiarity
LVDS interface host FPGA
No external VCO or clock reference is required
Integrated variable output cable drive
3.3V SMBus configuration interface
The integrated TXCLK PLL removes clock noise
SMALL 48PIN LLP PACKAGE
Industrial temperature range: -40 °C to 85 °C
illustrate
LMH0340/0040/0070/0050 SDI Serial Country FPGA Connectivity SER/DES supports FPGAs with FPGAs as part of the 5-bit LVDS interface product family. The host of the FPGA will be with the output of the LMH0340 in IP data formats that comply with the requirements of the DVB-ASI, SMPTE 259M-C, SMPTE 292M and SMPTE 424M standards. See also The standard for details is per-device support.
An interface between a 5-bit wide LVDS data bus, an LVDS clock and an SMBus interface between the SER (serial) and the FPGA. The LMH0340/0040/0070 SER equipment includes an integrated cable driver, which is fully compliant with all SMPTE specifications listed above. The LMH0050 has a CML output that can drive a driver for a differential transmission line or interface cable driver.
The FPGA's connected SER/DES family supports IP kits, allowing design engineers to quickly develop video applications using SER/DES products. The SER is housed in a small 48-pin LLP package.
Main specifications
Complies with SMPTE 424M, SMPTE 292M, SMPTE 259M-C and DVB-ASI outputs (see Table 1)
Typical power consumption: 440 mW
30 ps typical output jitter (HD, 3G)
apply
The SDI interfaces are:
camera
DVR
Video switcher
Video editing system