-
VDD=VDDQ=1.5V +/- 0.075V VDD = VDDQ = 1.5V + / - 0.075V
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Fully differential clock inputs (CK, /CK) operationå®å
¨å·®åæ¶éè¾å
¥ï¼CK / CKï¼çæä½
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Differential Data Strobe (DQS, /DQS)å·®åæ°æ®ééï¼DQS / DQSçï¼
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On chip DLL align DQ, DQS and /DQS transition with CKtransitionå¨é
åè¯ççDLL CKtransition DQï¼DQSå/ DQSçè¿æ¸¡
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DM masks write data-in at the both rising and fallingedges of the data strobe马å
å£ç½©åæ°æ®åä¸åï¼æ°æ®ééfallingedges
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All addresses and control inputs except data,data strobes and data masks latched on therising edges of the clockææçå°ååæ§å¶è¾å
¥æ°æ®ï¼æ°æ®ééåæ°æ®å£ç½©é¤å¤çéåæ¶éçtherisingè¾¹ç¼
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Programmable CAS latency 5, 6, 7, 8, 9, 10 and (11)supportedæ¯æå¯ç¼ç¨çCAS延è¿5ï¼6ï¼7ï¼8ï¼9ï¼10ï¼11ï¼
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Programmable additive latency 0, CL-1, and CL-2supportedå¯ç¼ç¨éå 延è¿0ï¼CL - 1åCL - 2supported
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Programmable CAS Write latency (CWL) = 5, 6, 7, 8å¯ç¼ç¨ä¸ç§é¢åå
¥å»¶è¿ï¼CWLï¼= 5ï¼6ï¼7ï¼8
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Programmable burst length 4/8 with both nibblesequential and interleave mode nibblesequentialå交é模å¼å¯ç¼ç¨ççªåé¿åº¦ä¸º4 / 8
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BL switch on the fly “åºæ¬æ³”å¼å
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8banks 8banks
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Average Refresh Cycle(Tcase of 0 °C~ 95 °C)å¹³åæ´æ°å¨æï¼TCASE 0 ° Cã95 ° Cï¼
- 7.8 µs at 0°C ~ 85 °C - 7.8å¾®ç§ä¸º0âã85â
- 3.9 µs at 85°C ~ 95 °C - 3.9å¾®ç§å¨85âã95â
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Auto Self Refresh supportedèªå¨èªå·æ°æ¯æ
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JEDEC standard 82ball FBGA(x4/x8), 96ball FBGA (x16) JEDECæ å82ball FBGAï¼x4/x8ï¼ï¼96balléç¨FBGAï¼X16ï¼
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Driver strength selected by EMRS EMRSéå®ç驱å¨å¼ºåº¦
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Dynamic On Die Termination supportedå¨æ模æ¯æç»æ¢
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Asynchronous RESET pin supportedæ¯æå¼æ¥å¤ä½å¼è
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ZQ calibration supportedæ¯æZQæ ¡å
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TDQS (Termination Data Strobe) supported (x8 only) TDQSï¼ç»æ¢æ°æ®ééï¼æ¯æï¼X8åªï¼
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Write Levelization supportedåLevelizationæ¯æ
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8 bit pre-fetch 8ä½é¢å
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This product in compliance with the RoHS directiveè¿ç¬¦åRoHSæ令ç产å