AD6677BCPZ 80 MHz bandwidth IF receiver
The AD6677 is an 11-bit, 250 MSPS intermediate frequency (IF) receiver designed to support multi-antenna systems in telecom applications requiring high dynamic range performance, low power, and small size.
The device includes a high-performance analog-to-digital converter (ADC) and a noise shaping requantizer (NSR) digital block. The ADC consists of a multistage, differential pipeline architecture with integrated output error correction logic, and the first stage of each ADC differential pipeline contains a wide bandwidth switched capacitor sampling network. An integrated reference simplifies design. The duty cycle stabilizer (DCS) compensates for fluctuations in the ADC clock duty cycle, allowing the converter to maintain excellent performance.
The output of the ADC is internally connected to the NSR block. Integrated NSR circuitry improves signal-to-noise ratio (SNR) performance in smaller bands within the Nyquist bandwidth. The device supports two different output modes, which can be selected via SPI. If the NSR feature is enabled, the AD6677 can achieve higher SNR performance within a limited portion of the Nyquist bandwidth while maintaining 11-bit output resolution when processing the output of the ADC.
The NSR block can be programmed to provide 22% or 33% of the bandwidth of the sample clock. For example, the AD6677 can achieve SNR up to 76.3 dBFS in a bandwidth of 55 MHz in 22% mode when the sampling clock rate is 250 MSPS; In 33% mode, it can achieve SNR of up to 73.5 dBFS in a bandwidth of 82 MHz.
When the NSR block is disabled, ADC data is provided directly to the output with 11-bit resolution. In this mode of operation, the AD6677 is capable of achieving SNR up to 65.9 dBFS over the entire Nyquist bandwidth. Therefore, the AD6677 can be used in telecom applications such as digital predistortion observation paths that require wider bandwidth.
The output data is sent directly to an external JESD204B serial output channel. This output is set to a current mode logic (CML) level. Supports a mode in which output encoded data is sent over a single channel (L = 1; F = 4). The device provides synchronous input control (SYNCINB± and SYSREF ±).
The AD6677 receiver is capable of digitizing a wide IF spectrum. This IF sampling architecture significantly reduces the cost and complexity of the device compared to traditional analog techniques or less integrated digital methods.
Flexible power-down options can significantly reduce power consumption when needed. Programmable overrange level detection is supported via a dedicated fast detect pin.
Product features
- The JESD204B output module can be configured with an integrated phase-locked loop (PLL) to support sample rates up to 5 Gbps per channel.
- The IF receiver includes an 11-bit, 250 MSPS ADC with a programmable noise shaping requantizer (NSR) function that improves the signal-to-noise ratio when the bandwidth is reduced to 22% or 33% of the sample rate.
- Supports optional RF clock input to simplify system board design.
- The patented differential inputs maintain excellent signal-to-noise ratio (SNR) performance at input frequencies up to 400 MHz.
- An on-chip 1 to 8 integer input clock divider and SYNC input support multi-device synchronization.
- Operates from a single 1.8 V supply.
- The standard serial port interface (SPI) supports a variety of product features and functions, such as control clock DCS, power-down mode, test mode, reference mode, overrange fast detection, and serial output configuration.
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- correspondence
- Diversity radio and smart antenna (MIMO) systems
- Multi-Mode Digital Receiver (3G)
TD-SCDMA、WiMAX、 WCDMA、
CDMA2000、GSM、 EDGE、LTE
- I/Q demodulation system
- Universal software defined radio
Microchip Centennial Electronic Technology (Shenzhen) Co., Ltd
Address: Shenzhen Futian District Huaqiang Road Huaqiang Plaza A Block 13H
Tel: 0755-83591082
Fax: 0755-83591083
Q Q：1051085817
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