AD9515It is a two-output clock distribution IC with low jitter and low phase noise for optimal implementationData convertersPerformance. The device is also suitable for other applications where phase noise and jitter are critical.
It provides two independent clock outputs, one LVPECL and the other that can be set to LVDS or CMOS levels. The LVPECL output operates at 1.6 GHz. The other output operates at 800 MHz in LVDS mode and 250 MHz in CMOS mode.
Each output has a programmable divider that can be programmed for integer divider ratios from 1 to 32. The phase of one clock output relative to the other clock outputs can be programmed through the divider phase selection function as coarse timing.
The LVDS/CMOS output provides delay characteristics with three selectable full-scale delay values (1.5 ns, 5 ns, and 10 ns), each with 16 steps of fine tuning.
The AD9515 requires no external controller to operate or set up. The device is programmed through 11 pins (S0 to S10) and 4 logic levels. The programming pin is internally biased to 1/3 VS. The VREF pin provides a 2/3 VS level. VS (3.3 V) and GND (0 V) provide two additional logic levels.
The AD9515 is ideal for data converter clock applications, using subpicosecond jitter to encode signals for optimal converter performance.
The AD9515 is available in a 32-lead LFCSP package and operates from a single 3.3 V supply over the −40°C to +85°C temperature range.
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Low jitter, low phase noise clock distribution
Provides clocks for high-speed ADC, DAC, DDS, DDC, DUC, MxFE
High-performance wireless transceivers
High-performance instrumentation
Broadband infrastructure
Automatic test equipment