AD6657A 65MHz bandwidth quad IF receiver
AD6657A is an 11-bit, 200 MSPS, quad-channel intermediate frequency (IF) receiver designed to support multi-antenna systems in telecommunications applications that require high dynamic range performance, low power consumption, and small form factor.
The device includes four high-performance ADCs and NSR digital modules. Each ADC adopts a multi-level, differential pipeline architecture and integrates output error correction logic. The first stage of the ADC differential pipeline contains a wide bandwidth switching capacitor sampling network. Integrated voltage reference simplifies design. The duty cycle stabilizer (DCS) compensates for fluctuations in the ADC clock duty cycle, allowing the converter to maintain excellent performance.
The outputs of each ADC are internally connected to the NSR module. Integrated NSR circuitry improves signal-to-noise ratio (SNR) performance in smaller frequency bands within Nyquist's bandwidth. The device supports two different output modes, which can be selected via an external MODE pin or SPI.
If the NSR feature is enabled, AD6657A can achieve higher SNR performance in a limited partial Nyquist bandwidth while maintaining 11-bit output resolution when processing the ADC's output. The NSR module can be programmed to provide 22%, 33%, or 36% of the bandwidth of the sample clock. For example, when the sampling clock rate is 185 MSPS, SNR up to 75.5 dBFS can AD6657A achieved in 22% mode over 40 MHz bandwidth; In 33% mode, it can achieve an SNR of up to 73.7 dBFS over a 60 MHz bandwidth; In 36% mode, SNR up to 70.0 dBFS can be achieved over 65 MHz bandwidth.
If the NSR module is disabled, the ADC data is provided directly to the output at 11-bit resolution. In this operating mode, AD6657A is able to achieve SNR of up to 66.5 dBFS over the entire Nyquist bandwidth. As a result, AD6657A can be used in telecommunications applications, such as using a wider bandwidth of digital predistortion observation paths.
After digital signal processing, the multiplexed output data is routed to two 11-bit output ports with a maximum data rate of 400 Mbps (DDR). These outputs are set to 1.8 V LVDS and support ANSI-644 levels. AD6657A receiver is capable of digitizing a wide mid-frequency spectrum. The receivers are designed to receive different antennas synchronously. This IF sampling architecture significantly reduces device cost and complexity compared to traditional analog techniques or less integrated digital methods.
Flexible shutdown options can significantly reduce power consumption. Programming of device setup and control is done using a three-wire SPI-compatible serial interface. The interface provides multiple operating modes to support board-level system testing.
AD6657A is available in a 144-pin lead-free 10 mm × 10 mm chip-scale ball grid array (CSP_BGA) package, is RoHS compliant, and is rated for an industrial temperature range of −40°C to +85°C.
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- 通信
- 分集无线电和智能天线(MIMO)系统
- 多模式数字接收机(3G)
WCDMA、LTE、CDMA2000
WiMAX、TD-SCDMA
- I/Q解调系统
- 通用软件无线电