AD7725BSZ
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AD7725BSZ

  • Category:converter
  • Product Name:16-bit sigma-delta ADC with programmable postprocessor
  • Manufacturers:AD
  • Production Batch Number:12+
  • Encapsulation:QFP44
  • Stock Status:There is stock
  • Stock Quantity:3450
  • Minimum order quantity: 1
  • Details:Click here to find pdf documentation for the AD7725BSZ
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  • Product introduction

The AD7725BSZ is a 16-bit sigma-delta ADC with a programmable post processor

The AD7725 is a complete 16-bit, sigma-delta analog-to-digital converter (ADC) with on-chip user-programmable signal conditioning. The modulator output is handled by three cascaded finite impulse response (FIR) filters and a user-programmable postprocessor in the post. The user has complete control over the filter response, filter coefficients, and decimation rate.

The AD7725 is specified for input bandwidths up to 300 kHz and has a maximum output word rate of 600 kHz. The input sample rate is set by a crystal oscillator or external clock and is rated at 9.6MHz with a maximum of 14.4MHz. The CLKIN frequency directly determines the maximum input bandwidth of the device and is the relationship between BW (max) = CLKIN/32. Conversion data is available through serial or parallel interfaces.

To program the postprocessor, an on-chip default filter or a user-defined filter can be loaded into the device in the form of a configuration file. User-defined filters can be loaded from a DSP with a serial interface or an external EPROM or from a DSP with a parallel interface.

A digital filter design package called the Filter Wizard can be leveraged to generate user-defined filter profiles. With this design package, the user can design different types of filters and generate the corresponding profiles for loading into the device.

Features and benefits

 

 


Programmable filtering:
- Any characteristics of up to 108-order FIR and/or IIR
Polynomial signal conditioning, up to the eighth order
Flexible programming modes:
- Import from DSP or external EPROM
- Parallel/serial interface
Internal default filter for evaluation

Programmable decimation and output word rates
Master clock frequency: 14.4 MHz maximum
Input range: 0 V to +4 V (single-ended) or ±2 V differential
AVDD, DVDD power supply: 5 V ± 5%
2.5 V on-chip reference
44-pin MQFP package
//www.chip100.com/

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Model Manufacturers lot number encapsulation illustrate
AD7725BSZ AD 12+ QFP44 16-bit sigma-delta ADC with programmable postprocessor

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