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DS90UR124QVS
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DS90UR124QVS

  • Category:Serializer-deserializer
  • Product Name:5 - 43MHz DC balanced 24-bit FPD - Link's second deserializer
  • Manufacturers:NXP
  • Production Batch Number:11+
  • Encapsulation:TQFP-64
  • Stock Status:There is stock
  • Stock Quantity:15000
  • Minimum order quantity: 1
  • Details:Click here to find pdf information on the DS90UR124QVS
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  • Product introduction

 peculiarity

 

  • Supports display with 18-bit color depth
  • Pixel clocks from 5MHz to 43MHz
  • Automotive grade products are AEC - Q100 Class 2 qualified
  • 24:1 interface compression
  • DC-balanced embedded clock supports AC-coupled data transmission
  • Capable of driving shielded twisted pair cables up to 10 meters long
  • No reference clock required (deserializer)
  • Complies with ISO 10605 ESD - HBM ESD structures greater than 8 kV
  • Supports hot plugging
  • EMI Reduction - The serial accepts the random shuffle of data on the spread-spectrum input serial link, and the deserializer provides an adjustable PTO (step-on) LVCMOS output
  • @高速BIST (built-in self-test) verifies the LVDS transmission path
  • Personal power-down control transmitter and reception
  • Supply voltage range: 3.3V ± 10%
  • 48-pin TQFP package, transmitter and receiver in 64-pin TQFP package
  • Temperature range: -40 °C to +105 °C
  • Backward compatibility mode with the DS90C241/DS90C124

 

illustrate

The DS90UR241/124 chipset converts a fully transparent data/control FPD-LINK II embedded clock information into a 24-bit parallel bus for LVDS serial data streams. The chipset is ideal for driving graphics data showing data that requires 18-bit color depth - RGB666 + HS, VS, DE + 3 additional general-purpose data channels. This single serial data stream simplifies the transmission of PCB traces and cables by eliminating skew issues between parallel data and clock paths, and transporting 24-bit buses. It saves system cost and shrinks the data path, which reduces the PCB layers, cable width, and connector size and pins.

The DS90UR241/124 uses FPD-Link's second LVDS high-speed I/O signal FPD-Link's second LVDS provides a low-power and low-noise environment for reliably transmitting data through the serial transmission path. By optimizing the serial output edge rate, EMI is further reduced over the operating frequency range.

In addition, the device uses pre-emphasis to improve the signal for the distance to no longer use lossy cables. Internal DC-balanced encoding/decoding is used to support AC-coupled interconnects. Using National Semiconductor's proprietary random lock, the serial parallel data deserializer is random and has no need for REFCLK.

 


apply

  • Information display in the center of the car
  • Car instrument display
  • Car head-up display
  • Remote camera-based driver assistance system

andDS90UR124QVSRelated ICs are:


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DS90C124QVS NXP 11+ TQFP-48 5 - 35MHz DC balanced 24-bit FPD - Link second serial
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DS90C241QVSX NXP 11+ TQFP-48 5 - 35MHz DC balanced 24-bit FPD - Link second serial
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DS90UR241QVSX NSC 09+ TQFP-48 5 - 43MHz DC balanced 24-bit FPD - Link's second serial
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DS99R101VS NSC 10+ TQFP 3 - 40MHz DC balanced 24-bit LVDS serializer
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