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DS90UR241QVSX
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DS90UR241QVSX

  • 所属类别：串行器-解串器
  • 产品名称：5 - 43MHz直流平衡的24位FPD - Link的第二串行
  • 厂商：NSC
  • 生产批号：09+
  • 封装：TQFP-48
  • 库存状态：有库存
  • 库存量：3000
  • 最低订购量：1
  • 详细资料：点击查找DS90UR241QVSX的pdf资料
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  • Product Introduction
peculiarity Supports display with 18-bit color depth Pixel clocks from 5MHz to 43MHz Automotive-grade products are AEC - Q100 Class 2 qualified 24:1 interface compression DC-balanced embedded clocks support AC-coupled data transmission Capable of driving shielded twisted pair cables up to 10 meters long No reference clock (deserializer) required Compliant with ISO 10605 ESD - HBM ESD structures greater than 8 kV Hot-swappable is supported Reduced EMI - Serial acceptance of data on the spread spectrum input serial link randomly shuffled, and the deserializer provides adjustable PTO (step-on) LVCMOS output @高速BIST (built-in self-test) validates the LVDS transmission path Personal power-down controls transmitter and reception Supply voltage range: 3.3V ± 10% 48-pin TQFP package, 64-pin TQFP package for transmitter and receiver Temperature range: -40°C to +105°C Backward compatibility mode with DS90C241/DS90C124 illustrate The DS90UR241/124 chipset converts into a fully transparent data/control FD-LINK II 24-bit parallel bus for LVDS serial data streams with embedded clock information. The chipset is ideal for driving graphics data display requires 18-bit color depth - RGB666 + HS, VS, DE + 3 additional universal data channels. This single serial data stream simplifies the transmission of PCB traces and cables over the 24-bit bus by eliminating the problem of bias between parallel data and clock paths. It saves system costs and narrows the data path, which reduces the size and pins of PCB layers, cable widths, and connectors. DS90UR241/124 Uses FPD-Link's 2nd LVDS High-Speed I/O Signal FPD-Link's 2nd LVDS provides a low-power and low-noise environment for reliably transmitting data over a serial transmission path. By optimizing the serial output edge rate operating frequency range, EMI is further reduced. In addition, the device emphasizes the signal to increase the distance to no longer use the lossy cable. Internal DC balanced encoding/decoding is used to support AC-coupled interconnects. Using National Semiconductor's proprietary random lock, the serial parallel data deserializer is random and does not require REFCLK. apply Central information display of the car Automotive instrument display Car head-up display Remote camera-based driver assistance system

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Model Manufacturers lot number encapsulation illustrate
DS90C124QVS NXP 11+ TQFP-48 5 - 35MHz DC-balanced 24-bit FPD-Link 2nd Serial
DS90C124QVSX NXP 11+ TQFP-48 5 - 35MHz DC-balanced 24-bit FPD-Link 2nd Serial
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