MFRC50001T/0FE,112

3.1 Introduction

• Highly integrated analog circuitry for demodulating and decoding card responses
• Buffered output drivers enable antenna connection with minimal external component count
• Approaching working distances of up to 100 mm
• Supports ISO/IEC 14443 A parts 1 to 4
• Supports the MIFARE Classic protocol
• Crypto1 and secure non-volatile internal key memory
• The pins are compatible with the CLRC632, MFRC530, MFRC531, and SLRC400
• Parallel microprocessor interface with internal address latch and IRQ lines
• Flexible interrupt handling
• Automatic detection of parallel microprocessor interface types
• 64-byte send and receive FIFO buffers
• Hard reset low power function
• Software-triggered shutdown mode
• Programmable timer
• Unique serial number
• User-programmable startup configuration
• Bit-oriented and byte-oriented framing
• Separate power pins for analog, digital, and transmitter modules
• The internal oscillator buffer is optimized for low phase jitter with a 13.56 MHz quartz connection
• Clock frequency filtering
• The transmitter operates at 3.3 V for both near and near applications