AD6672BCPZ-250 IF receiver
The AD6672 is an 11-bit IF receiver with sampling rates up to 250 MSPS designed to provide a solution for low cost, small size, wide bandwidth, versatile communication applications.
The ADC core uses a multistage, differential pipelined architecture with integrated output error correction logic. The ADC has wide bandwidth inputs and supports a variety of user-selectable input ranges. An integrated reference simplifies design. A duty cycle stabilizer can be used to compensate for fluctuations in the ADC clock duty cycle, allowing the converter to maintain excellent performance.
The core output of this ADC is internally connected to a noise shaping requantizer (NSR) block. The device supports two output modes, selectable through the serial port interface (SPI). If the NSR feature is enabled, the AD6672 can achieve higher SNR performance in the limited Nyquist bandwidth region while maintaining 11-bit output resolution when processing the output of the ADC. The NSR module can be programmed to provide up to 33% of the sample clock bandwidth. For example, with a sample clock rate of 250 MSPS, the AD6672 achieves SNR up to 73.6 dBFS at 82 MHz bandwidth at 185 MHz fIN.
If the NSR block is disabled, ADC data is provided directly to the output with 11-bit output resolution. In this mode of operation, the AD6672 achieves SNR up to 66.6 dBFS over the entire Nyquist bandwidth.
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- correspondence
- Diversity radio and smart antenna (MIMO) systems
- Multi-mode digital receiver (3G) WCDMA, LTE, CDMA2000 WiMAX, TD-SCDMA
- I/Q demodulation system
- Universal software defined radio