The AD9691 is a dual, 14-bit, 1.25 GSPSAnalog-to-digital converters (ADC)。 该器件内置片内缓冲器和采样保持电路，专门针对低功耗、小尺寸和易用性而设计。 该器件设计用于高达1.5 GHz的宽带模拟信号采样。
This dual ADC core uses a multistage, differential pipelined architecture with integrated output error correction logic. Each ADC has wide bandwidth inputs that support a variety of user-selectable input ranges. An integrated reference simplifies design.
各ADC数据输出内部连接到两个数字下变频器(DDC)。 每个DDC含有4个级联的信号处理级： 一个12位频率转换器(NCO)和四个半带抽取滤波器。
In addition to the DDC block, the AD9691 has additional features that simplify automatic gain control (AGC) in communication receivers. Using the ADC's fast sense output bits, a programmable threshold detector monitors the input signal power. If the input signal level exceeds a programmable threshold, the quick detect indicator goes high. The very low latency of this threshold indicator allows the user to quickly lower the system gain to avoid overrange at the ADC input.
The high-speed serial output of JESD204B Subclass 1 can be set to a variety of single, dual, quad, or octal configurations, depending on the DDC configuration and acceptable lane rate of the receiving logic. SYSREF ± input pins provide multi-device synchronization support.
The AD9691 is available in an 88-lead lead-free LFCSP package and is specified over the industrial temperature range of −40°C to +85°C.
Product features
- 低功耗模拟内核，14位、1.25 GSPS双通道Analog-to-digital converters(ADC), 1.9 W per channel.
- Wide full power bandwidth supports sampling of IF signals up to 1.5 GHz.
- Buffered inputs with programmable inputs simplify filter design and implementation.
- A flexible serial port interface (SPI) controls a variety of product features and functions to meet specific system requirements.
- Programmable fast overrange detection. /li>
- 12 mm × 12 mm, 88-pin LFCSP.
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- Communications (wideband receivers and DMD)
- Instrumentation (spectrum analyzers, network analyzers, integrated RF test solutions)
- DOCSIS 3.x CMTS upstream receive path
- High-speed data acquisition system