Full of dry goods, in-depth interpretation of the key indicator of high-speed ADC - conversion error rate

High-speed analog-to-digital converters (ADCs) have some inherent limitations that can occasionally cause rare conversion errors beyond their normal function. However, many actual sampling systems do not allow high ADC conversion error rates. Therefore, quantizing the frequency and amplitude of the high-speed analog-to-digital conversion error rate (CER) is very important.

 

High-speed or GSPS ADCs (Gigabit Sampling ADCs per second) and relatively sparse conversion errors not only make them difficult to detect but also make the measurement process very time-consuming. This duration often exceeds milliseconds, reaching hours, days, weeks, or even months. To help reduce this time-consuming testing burden, error rates can be estimated with certainty at a certain level of "confidence" while maintaining the quality of results.

Similar to the digital equivalent of BER in serial or parallel digital data transmission, CER is the ratio of the number of conversion errors to the total sample size.但是，BER和CER之间有一些截然不同之处。数字数据流中的BER测试采用长伪随机序列，该序列可于发送器中在传输两端使用常用种子值来启动。接收器预期将收到理想的传输。通过观察接收数据与理想数据的差异，便可精确计算出BER。两端之间伪随机序列数据中的失配(基于种子值)即视为误码。

 

Unlike CER, error measurement is not as simple as a simple numerical comparison. Because ADC conversion always involves small nonlinearity, as well as system noise and jitter, it is not always possible to determine the exact difference between expected and actual data. Instead, an error threshold needs to be established to determine the boundary between conversion errors and samples with allowable expected noise. This differs from digital BER and does not provide an exact comparison of the expected data sent and received. Instead, the error magnitude of the sample must first be quantified, and only then determined whether it is a conversion error or within the expected nonlinear range of the converter and system. The bit-error rate of the digital interface on the ADC backend must be lower than the converter's core CER, so it cannot be ignored. If not, data output transmission errors will override the CER and become the main source of error.

A common cause of conversion errors in high-speed ADCs is a phenomenon called metastability.高速ADC在将模拟信号转换为数字值的转换过程中，往往会在不同阶段使用多个梯级比较器。如果比较器无法确定模拟输入是高于还是低于其参考点时，就会产生可能导致出现错误代码的亚稳态结果。当两个比较器的输入之差幅度非常小或为零时，就可能发生这种情况，此时无法进行正确比较。由于此错误值会沿着流水线传播，因此ADC可能产生重大的转换错误。

 

When the input for differential simulation is a relatively large positive or negative value, the comparator can quickly calculate the difference and provide a clear decision. When the difference value is small or zero, the comparator takes much longer to make a decision. If the comparator outputs latch before this decision point, a metastable result will be produced.

 

Some design solutions can mitigate this problem.

First, the comparator is designed to have a very small uncertainty range, forcing it to make accurate decisions within the maximum possible simulated input conditions. However, this can lead to increased circuit power and design size.

The second method is to delay comparator sampling time as much as possible, giving the analog input the longest time to establish the known comparator output value. However, this method has multiple limitations, as the delay can only last until the current sampling time ends, after which the comparator must continue processing the next sample.

The third method uses intelligent error detection and correction algorithms that digitally compensate for uncertainties introduced by comparators in subsequent stages of the high-speed ADC conversion process. When a comparator fails to make a decision within the maximum allowable time, logic can detect the deficiency. This information can then be attached to relevant samples for future internal adjustments. When this alarm is identified, post-processing steps can be used to correct the error before the sample is output from the converter. This can be seen from the AD9625 in Figure 1, a 12-bit, 2.5GSPS ADC from ADI.

Figure 1: Comparator uncertainty can be identified during the analog-to-digital conversion process of the AD9625. Execute the calibration command in subsequent steps to correct the sample, then output from the converter.

CER Confidence (CL) refers to the extrapolation of future errors without being precise to a specific failure rate. This reduces the total number of samples obtained for a given CER, but at the cost of not guaranteeing 100% certainty.从数学角度来说，要达到绝对100%的确定性，需要取得无限持续时间内的样本。因此，根据行业经验，95%的置信度已经相当接近已知值，并且实现了不确定性和测量时间之间的平衡。如果将测试重复一百次，则有95次可以准确识别误码率。有时工程师会误认为一旦在测试期间检测到误差，该过程就会结束并找到最终的CER。这既不准确也不完整。无论过程中是否有误差，转换误差率及相关的置信度都可以测试。但是，如果在给定置信度下检测到误差，则与没有错误时的样本数相比，必须增加测量的样本数量。

The above formula provides the natural logarithmic mathematical relationship expression for confidence level, bit error rate, and sample size. Where: N is the number of samples to be measured; CER is the conversion bit error rate; CL is the confidence level; E is the number of detected errors.

 

When no error is detected, the formula is simplified: the term on the right equals zero, and the result depends only on the term on the left. When CL is 95% and no error is detected, the required sample size is only about the reciprocal of the expected CER multiplied by 3. Measuring 100% confidence, i.e., CL = 1.0 for any CER value, mathematically requires obtaining -ln(0) infinitely infinite sample counts (N).

The conversion error margin in high-speed ADCs is critical; some errors are more significant than others. For example, one or two least effective bit (LSB) errors may fall within the system's expected noise floor and may not even affect instantaneous performance. However, highest significant significant bit (MSB) errors, or even full-scale errors, can cause system failure events. Therefore, CER testing requires a mechanism or threshold to determine the severity of errors during conversion.

 

The error threshold for conversion should include known linearity deficiencies of the ADC, as well as clock jitter and other system noise beyond the converter's capabilities.对于任何给定样本，这些通常会累加为14位ADC的4或5个最低有效位(LSB)或16～32个代码。根据ADC分辨率、系统性能和应用的误码率要求，该值的大小可能略有不同。使用此误差带与理想值进行比较后，超出此限值的样本将被视为转换错误。在传统视频ADC中，此错误被称为“闪码”，因为它会在视频屏幕上产生亮白色像素闪烁。可接受的转换器误码率很大程度上取决于信号处理系统和系统误差容差要求。

 

Historically, the conversion error rate of GSPS ADCs has generally not been lower than 1e-14. The 1e-15 error rate means the converter should not have conversion errors within the 1e15 sample range. Although these numbers seem large, with today's advanced converter technology's high sampling rates, CER testing is still achievable. However, for a 125MSPS converter with an 8ns sampling rate, 1e15 sampling will take 800,000 seconds (1e15*8ns), which is 9.24 days. To achieve 95% CL in these bit error rates, the average sampling duration must be multiplied by 2.996.

Figure 2 shows how to test the internal ADC core CER. When sampling at or near the ADC's maximum encoding rate, a relatively slower frequency sine wave can be used as the analog input. Analog input signals should be planned so that, ignoring system noise, the expected absolute difference between two adjacent samples does not exceed 1LSB code. Ideally, the analog input signal should be slightly larger than the full scale to allow all ADC code to be used. Analog input and code sampling rates should be calculated to establish longer consistency cycles, whereas ADCs do not perform consistent sampling at the same code level.

Figure 2: Two sampling scenarios for CER testing. The top case samples analog signals at a rate slightly faster than Fs/2, with only one sample compared every other sample. Ideally, the difference between two consecutive samples should not exceed one LSB code. The following scenario involves oversampling relatively slow analog inputs so that differences between two adjacent samples do not exceed one LSB code.

The system uses a counter to track when the amplitude difference between two adjacent samples exceeds the threshold limit and counts this as a conversion error. This counter must retain the cumulative total of errors throughout the entire testing process. To ensure the system operates as expected, the relationship between the error magnitude and ideal conditions should also be recorded. The time required for testing will be based on sampling rate, required test CER, and required confidence (Figure 3).

Typical converter architectures can achieve some system-acceptable measurement conversion bit error rates, and new designs and error detection algorithms are driving better performance at the limits. ADI's 12-bit 2.5 GSPS ADC AD9625 hierarchical comparison pipeline core uses proprietary technology to detect ADC conversion errors during the early stages of the pipeline, then process and correct later errors. This achieves industry-leading measurement CERs on 12-bit GSPS ADCs that outperform the 1e-15 with 95% confidence.