YPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "//www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">

AVR Enhanced RISC Structure - Global spot and futures advantage channel for imported component suppliers
home page>News> latest arrival >

AVR-enhanced RISC structure

Author:Administrator Source:Site Views:637 Release time:2012/5/21 17:42:52

Main Specifications / Special Features:

  • The ATmega48/88/168 are low-power 8-bit CMOS microcontrollers based on the AVR-enhanced RISC architecture
  • Due to its advanced instruction set and single-cycle-cycle instruction execution time, the ATmega48/88/168 has a data throughput rate of up to 1MIPS/MHz, which can alleviate the contradiction between power consumption and processing speed of the system
  • The AVR core has a rich instruction set and 32 general-purpose operating registers
  • All registers are connected directly to the arithmetic logic unit (ALU), allowing an instruction to access two independent registers simultaneously in a single clock cycle, greatly improving code efficiency and providing up to 10 times the data throughput rate of ordinary CISC microcontrollers
  • Peculiarity:
    • 4K/8K/16K bytes of in-system programmable Flash (with readable during programming, i.e. RWW), 256/512/512 bytes of EEPROM, 512/1K/1K bytes SRAM, 23 general-purpose I/O port lines, 32 general-purpose operating registers, three flexible timers/counters with comparison mode
    • (T/C), on-chip/off-chip interrupt, programmable serial USART, byte-oriented two-wire serial interface
    • One SPI serial port, six 10-bit ADCs (eight 10-bit ADCs in TQFP and MLF packages), a programmable watchdog timer with on-chip oscillator, and five software-selectable power-down modes
    • In idle mode, the CPU stops working, while SRAM, T/C, USART, the two-wire serial interface, the SPI port, and the interrupt system continue to operate
    • In power-down mode, the crystal oscillator stops oscillating, all functions stop working except interrupts and hardware resets, and the contents of the registers are maintained; In power-down mode, the asynchronous timer continues to operate to allow the user to maintain the time reference while the rest of the device sleeps
    • The ADC noise suppression mode stops the CPU and all I/O blocks while the asynchronous timer and ADC continue to operate to reduce switching noise during ADC conversion
    • Standby mode when the oscillator operates
    • The rest of the sleep allows the device to consume very little current while providing fast start-up
    • The ATmega48/88/168 are manufactured using Atmel's high-density non-volatile memory technology