The PN512 internal transmitter has ISO/IEC 14443A/MIFARE read/write mode to drive read/write antennas and transponders without the need for additional active circuitry; The read-write antenna is designed for communication with ISO/IEC 14443A/MIFARE cards. The receiver section demodulates and decodes signals from ISO/IEC 14443A/MIFARE compliant cards and transponders in a stable and efficient manner. The digital part handles complete ISO/IEC 14443A framing and error detection (parity and CRC).
The PN512 supports MIFARE 1K or MIFARE 4K simulation products. The PN512 supports two-way contactless communication with MIFARE's high transmission rate (up to 424 kb/s).
The PN512 transceiver IC has a FeliCa read/write mode and supports FeliCa communication schemes. The receiver provides a stable and efficient demodulation and decoding circuit solution, compatible with FeliCa encoded signals. The digital part handles FeliCa framing and error detection, such as CRC. The PN512 supports two-way contactless communication with FeliCa's high transmission rates (up to 424 kb/s).
PN512 supports all levels of ISO/IEC 14443B read-write communication scheme, provided that additional components (e.g., oscillators, power supplies, coils, etc.) are properly deployed and that standard protocols (e.g., ISO/IEC 14443-4 and/or ISO/IEC 14443B anti-interference) are properly deployed.
In card operation, the PN512 transceiver IC responds to read and write commands according to the FeliCa or ISO/IEC 14443A/MIFARE card interface scheme. The PN512 generates a digital load modulation signal that, in conjunction with external circuitry, sends the response signal back to the reader. Complete security card functionality can only be provided if it is used with a security IC via the S²C interface.
In addition, the PN512 transceiver IC communicates directly with NFCIP-1 devices in NFCIP-1 mode. NFCIP-1 mode offers a variety of communication modes and transmission rates up to 424 kb/s in accordance with Ecma 340 and ISO/IEC 18092 NFCIP-1 standards. The digital section handles complete NFCIP-1 framing and error detection.
Integration of various host controller interfaces:
- 8-bit parallel interface
- SPI interface
- Serial UART (similar to RS232, voltage level depends on pad supply voltage)
- I²C interface.
The purchaser of this NXP IC must have the appropriate third-party patent license.
Features and benefits
- Highly integrated analog circuitry for demodulating and decoding responses
- The buffered output driver connects the antenna with the minimum number of external components
- Integrated RF level detector
- Integrated data pattern detector
- Supports ISO/IEC 14443 A/MIFARE
- Supports ISO/IEC 14443 B read/write mode
- Typical operating distances of up to 50 mm in read-write mode depend on antenna size and tuning
- In NFCIP-1 mode, the typical operating distance is up to 50 mm, depending on antenna size, tuning, and power supply
- In operating mode, the typical operating distance of an ISO/IEC 14443A/MIFARE card or FeliCa card is approximately 100 mm, depending on antenna size, tuning and external field strength
- MIFARE 1K or MIFARE 4K emulation encryption is supported in read-write mode
- Supports ISO/IEC 14443A high communication transmission rates (212 kb/s and 424 kb/s)
- Contactless communication according to FeliCa scheme (212 kb/s and 424 kb/s)
- Integrated RF interface for up to 424 kb/s NFCIP-1
- S²C interface
- Additional power can be supplied directly to smart card ICs connected via S²C
- Supported host interfaces:
- SPI up to 10 Mb/s
- I²C-bus interface (up to 400 kBd in fast mode and up to 3400 kBd in high-speed mode)
- RS232 serial UART up to 1228.8 kBd, voltage level depends on pin supply voltage
- Integrated/non-integrated address latch enabled 8-bit parallel interface
- FIFO buffer, handles 64-byte send and receive
- Flexible interrupt mode
- Hard reset low power function
- A shutdown mode is provided through software
- Programmable timer
- Internal oscillator for connection to 27.12 MHz quartz crystals
- Supply voltage: 2.5 V to 3.6 V
- CRC coprocessor
- Programmable I/O pins
- Internal self-test