AD9652BBCZRL7-310

This dual-channel ADC core features a multi-level, pipeline architecture with integrated output error correction logic. A high-performance on-chip buffer and internal reference source simplify external driver circuit interfaces while maintaining the ADC's outstanding performance.

The AD9652 supports input clock frequencies up to 1.24 GHz and uses 1, 2, 4, and 8 integer clock dividers to generate ADC sampling clocks. A duty cycle stabilizer is provided to compensate for fluctuations in the ADC clock duty cycle. The 16-bit output data from each ADC (with overrange bits) is interleaved with dual data rate (DDR) clocks on separate LVDS output ports. Setup and control programming is done using a three-wire SPI-compatible serial interface.

The AD9652 is available in a 144-pin CSP_BGA package and is rated for an industrial temperature range of −40 °C to +85 °C. This product is protected by a pending U.S. patent.

Product features: 

1. 集成双通道、16位310 MSPS ADC。
2. 片内缓冲器简化ADC驱动器接口。
3. 采用3.3 V和1.8 V电源供电，数字输出驱动器则采用独立电源供电，以支持LVDS输出。
4. 取得专利的差分输入在最高至485 MHz的输入频率下仍保持出色的信噪比(SNR)性能。
5. SYNC输入可在多个设备之间实现同步。
6. 三线式、3.3 V或1.8 V SPI端口，用于寄存器编程和回读。

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• 军用雷达和通信
• 多模式数字接收机（3G或4G）
• 测试和仪器仪表
• 智能天线系统