AD9652BBCZRL7-310

AD9652It is a dual, 16-bit sample rate up to 310 MSPSAnalog-to-digital converters(ADC)。 It is designed to support demanding, high-speed signal processing applications that require excellent dynamic range over a wide input frequency range (up to 465 MHz). Its excellent low noise floor (-157.6 dBFS) and spurious-free dynamic range (SFDR) performance (over 85 dBFS, typical) enable resolution of low-level signals in the presence of large signals.

This dual ADC core uses a multistage, pipelined architecture with integrated output error correction logic. The high-performance on-chip buffer and internal reference simplify interfacing with external driver circuitry while maintaining the ADC's excellent performance.

The AD9652 supports input clock frequencies up to 1.24 GHz and uses 1, 2, 4, and 8 integer clock dividers to generate the ADC sample clock. A duty cycle stabilizer is provided to compensate for fluctuations in the ADC clock duty cycle. The 16-bit output data from each ADC (with overrange bits) is interleaved with the dual data rate (DDR) clock at a separate LVDS output port. Setup and control programming is accomplished using a 3-wire SPI-compatible serial interface.

The AD9652 is available in a 144-lead CSP_BGA package and is specified over the industrial temperature range of −40°C to +85°C. This product is protected by a pending U.S. patent.

Product features 

1. Integrated dual, 16-bit, 310 MSPS ADC.
2. On-chip buffers simplify ADC driver interface.
3. It operates from 3.3 V and 1.8 V supplies, while the digital output driver operates from a separate supply to support LVDS outputs.
4. The patented differential input maintains excellent signal-to-noise ratio (SNR) performance at input frequencies up to 485 MHz.
5. The SYNC input enables synchronization between multiple devices.
6. 3-wire, 3.3 V or 1.8 V SPI port for register programming and readback.

apply

• Military radar and communications
• Multi-mode digital receiver (3G or 4G)
• Testing and instrumentation
• Smart antenna system