The AD9763/AD9765/AD9767 are dual-port, high speed, dual, 10-/12-, 14-bit CMOS DACs, each integrating two high quality TxDAC+ ® cores, a voltage reference, and digital interface circuitry in a small 48-lead LQFP package. These devices provide excellent ac and dc performance while supporting update rates up to 125 MSPS.
The AD9763/AD9765/AD9767 are optimized for I and Q data processing in communications applications. The digital interface contains two double-buffered latches as well as control logic. Independent write inputs allow data to be written to the two DAC ports independently of each other. A separate clock controls the update rate of each DAC.
The mode control pin allows the AD9763/AD9765/AD9767 to interface with two separate data ports or to a single interleaved high speed data port. In interleaved mode, the input data stream is demultiplexed into the original I data and Q data and then latched. The I data and Q data are then converted by two DACs and updated at half the input data rate.
The GAINCTRL pin allows the full-scale current (I) of both DACs to be set in two modesOUTFS)。 You can set the IOUTFS of each DAC independently with two external resistors, or you can set the IOUTFS of two DACs with one external resistor. For important datecode information about this feature, see the Gain Control Mode section.
These DACs use a segmented current source architecture combined with proprietary switching techniques to reduce surge energy and maximize dynamic accuracy. Each DAC provides a differential current output to support single-ended or differential applications. The two DACs of the AD9763, AD9765, or AD9767 can be updated simultaneously and can deliver a nominal full-scale current of 20 mA. Full-scale current matching between DACs can be within 0.1%.
The AD9763/AD9765/AD9767 are manufactured on an advanced, low cost CMOS process and operate from a single 3.3 V to 5 V supply and consume 380 mW.
Product Focus
- The AD9763/AD9765/AD9767 are pin-compatible, dual 8/10/12/14-bit resolution TxDAC families.
- Dual, 10/12/14-bit, 125 MSPS DAC. Each device features a pair of high-performance DACs optimized for low distortion performance for flexible transmission of I and Q information.
- Matching. Gain matching is typically 0.1% of full scale with better than 0.02% offset error.
- Low power consumption. Complete CMOS dual DAC capability operates from a single 3.3 V to 5 V supply and consumes 380 mW. The DAC full-scale current can be reduced, allowing operation at lower power consumption and sleep mode during low-power idle periods.
- On-chip reference. The AD9763/AD9765/AD9767 have an internal 1.20 V temperature compensated bandgap reference.
- Dual 10/12/14-bit inputs. The AD9763/AD9765/AD9767 each have a flexible two-port interface that allows data to be entered in a dual or interleaved manner.
apply
correspondence
base station
Digital synthesis
Quadrature modulation
Three-dimensional ultrasound