AD9528is a two-stage PLL with integrated JESD204B SYSREFgenerator, which can be used for multi-device synchronization. The first stage of the phase-locked loop (PLL1) enables input reference conditioning by reducing jitter of the system clock. The second stage PLL (PLL2) provides a high-frequency clock for lower integral jitter from the clock output driver and lower wideband noise. The external VCXO provides the low noise reference voltage required by PLL2 to meet demanding phase noise and jitter requirements for acceptable performance. The on-chip VCO is tuned over a frequency range of 3.450 GHz to 4.025 GHz. The integrated SYSREF generator outputs single, N, or continuous signals and synchronizes with the PLL1 and PLL2 outputs to align the time of multiple devices.
The AD9528 generates two outputs (output 1 and 2) up to 1.25 GHz and 12 outputs up to 1 GHz, each configured to output directly from PLL1, PLL2, or the internal SYSREF generator. Each of the 14 output channels contains a divider with digital phase coarse tuning and an analog trimmed phase delay block, allowing all 14 outputs to have a high degree of flexibility in timing alignment. The AD9528 can also be used as a flexible dual input buffer to distribute 14 device clocks and/or SYSREF signals. At power-up, the AD9528 sends VCXO signals directly to outputs 12 and 13 to serve as power-up ready clocks.
Note Throughout the data sheet, dual-function pin names refer to the applicable relevant function.
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- High-performance wireless transceivers
- LTE and multicarrier GSM base stations
- Wireless and broadband infrastructure
- Medical instruments
- Provide clocks for high-speed ADC, DAC, DDS, DDC, DUC, MxFE; JESD204B is supported
- Low jitter, low phase noise clock distribution
- Automated Test Equipment (ATE) and high-performance instrumentation