AD9690BCPZ-500

AD9690It is a 14-bit, 1 GSPSAnalog-to-digital converters(ADC)。 The device includes an on-chip buffer and sample-and-hold circuitry designed for low power, small size, and ease of use. The device is designed for sampling wideband analog signals up to 2 GHz. The AD9690 is optimized for wide input bandwidth, high sample rate, excellent linearity, and low power consumption in a small package. 

The ADC core uses a multistage, differential pipelined architecture with integrated output error correction logic. The ADC has wide bandwidth inputs and supports a variety of user-selectable input ranges. An integrated reference simplifies design. 

Both the analog input and the clock signal are differential. The ADC data output is internally connected to two digital downconverters (DDCs). Each DDC contains four cascaded signal processing stages: a 12-bit frequency converter (NCO) and four half-band decimation filters. 

In addition to the DDC block, the AD9690 has additional features that simplify automatic gain control (AGC) in communications receivers. Using the ADC's fast sense output bits, a programmable threshold detector monitors the input signal power. If the input signal level exceeds a programmable threshold, the quick detect indicator goes high. The very low latency of this threshold indicator allows the user to quickly lower the system gain to avoid overrange at the ADC input. 

The user can configure the subclass 1 JESD204B high-speed serial output as 1, 2, or 4 lanes, depending on the DDC configuration and the acceptable channel rate of the receiving logic. Multi-device synchronization support is provided through SYSREF ± and SYNCINB ± input pins. 

The AD9690 has flexible power-down options that significantly reduce power consumption when needed. These features are programmable via a 1.8 V to 3.3 V 3-wire SPI. 

The AD9690 is available in a 64-lead lead-free LFCSP package and is specified over the industrial temperature range of -40°C to +85°C. This product is protected by a U.S. patent. 

Product features

1. Wide full power bandwidth supports sampling of IF signals up to 2 GHz
2. Buffered inputs with programmable inputs simplify filter design and implementation.
3. Two integrated wideband decimation filters and digitally controlled oscillator (NCO) modules support multiband receivers.
4. A flexible serial port interface (SPI) controls a variety of product features and functions to meet specific system requirements.
5. Programmable fast overrange detection.
6. 9 mm × 9 mm, 64-pin LFCSP.

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• correspondence
• Multi-band, multi-mode digital receivers 3G/4G, TD-SCDMA, W-CDMA, GSM, LTE
• Universal software defined radio
• Ultra-wideband satellite receiver
• Instrumentation
• radar
• Signals Intelligence (SIGINT)
• DOCSIS 3.0 CMTS upstream receive path
• HFC digital reverse path receiver