- Support for input PCLK from 10 MHz to 43 MHz
- Data throughput from 160 Mbps to 688 Mbps
- Single differential pair interconnect
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Bidirectional control of the interface channel with I 2 Support C
- Embedded DC balanced coding supports AC-coupled clock interconnects
- Capable of driving shielded twisted pair up to 10 meters
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I 2 C-compatible serial interface
- A single hardware device solves the pin
- The 16-bit data payload CRC (Cyclic Redundancy Check) checks the integrity of the data
- 6 programmable GPIOs
- The lock output report pin and the AT-speed BIST self-diagnostic function to verify the integrity of the link
- Integrated termination resistors
- 1.8V or 3.3V compatible with parallel bus interface
- Operates from a single 1.8V supply
- The ESD of the ISO 10605 standard is compatible with the ESD of IEC 61000-4-2
- Automotive grade products: AEC - Q100 standard level 2 qualified
- Temperature range -40 °C to +105 °C
- There is no reference clock on the deserializer
- Programmable receive equalization
- EMI/EMC mitigation
- Programmable spread spectrum (SSCG) output of DES
- Receive interleaved output of DES
illustrate
The DS90UB901Q/DS90UB902Q chipsets provide a high-speed forward channel and a linked FPD-III interface in a single differential-to-bidirectional control channel for data transmission. It is a direct connection between the camera system and the host controller/electronic control unit (ECU) of the car for the serializer/deserializer. The primary transmission sends 16-bit image data, in a single high-speed serial data stream, along with a low-latency bidirectional control channel that supports my transportation 2 C. CRC (Cyclic Redundancy Check) containing a 16-bit payload is an optional data integrity option to monitor transmission link errors. Using state-of-the-art embedded clocking technology, which allows for transparent full-duplex communication in a single differential-to-transparent, video blanking interval relies on carrying asymmetric bidirectional control information. This single serial data stream simplifies the transmission of data buses by eliminating skews between parallel data and clock paths. This results in significant savings in system cost and narrowing the data path, which reduces PCB layers, cable width, and connector size and pins.
In addition, the deserializer input provides equalization control from the media over longer distances to compensate for losses. Internal DC-balanced encoding/decoding is used to support AC-coupled interconnects.
A serialized standby feature provides the ability to wake up remotely with signals from remote devices in a low-power-saving mode.
The serializer is available in a 32-pin LLP (5mm x 5mm) package and the deserializer is available in a 40-pin LLP (6mm x 6mm) package.
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- Automotive vision systems
- Rear-viewing, side-looking camera
- Lane departure warning
- Parking assistance
- Blind spot viewing
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