HMC987LP5E 1:9 fan-out buffers are designed for low-noise clock distribution. The device is designed to generate a relative square wave output with a rise/fall time of less than 100 ps. HMC987LP5E have low skew and jitter outputs and fast rise/fall times, allowing for control of low-noise switching functions in downstream circuits such as mixers, ADCs/DACs, or SERDES devices. In these applications, the noise floor is especially important when the clock network bandwidth is wide enough to allow for square wave switching. The HMC987LP5E output is driven at 2 GHz and has a noise floor of -166 dBc/Hz, which equates to a jitter density of 0.6 asec/rtHz, or 50 fs over the 8 GHz bandwidth.
The input stage can be single-ended or differentially driven in a variety of signal formats (CML, LVDS, LVPECL, or CMOS), as well as AC or DC coupling. The input stage also has an adjustable input impedance. The device integrates 8 LVPECL outputs with adjustable swing/power levels and 1 CML output in 3 dB steps.
Each output stage can be enabled or disabled by controlling the hardware control pin or serial port interface to conserve power when not needed.
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SONET、光纤通道、GigE时钟分配
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ADC/DAC时钟分配
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低偏斜和抖动时钟或数据扇出
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无线/有线通信
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电平转换
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高性能仪器仪表
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医疗成像
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单端至差分转换