HMC987LP5E 1:9 fan-outbumperDesigned for low noise clock distribution. The device is designed to generate a relative square wave output with rise/fall times of less than 100 ps. The HMC987LP5E features low skew and jitter outputs and fast rise/fall times, enabling low-noise switching of downstream circuits such as mixers, ADCs/DACs, or SERDES devices. In these applications, the noise floor is especially important when the clock network bandwidth is wide enough to allow square wave switching. The output of the HMC987LP5E is driven at 2 GHz and has a noise floor of -166 dBc/Hz, which corresponds to a jitter density of 0.6 asec/rtHz, or 50 fs in an 8 GHz bandwidth.
The input stage can be single-ended or differentially driven, available in a variety of signal formats (CML, LVDS, LVPECL, or CMOS), and AC- or DC-coupled. The input stage also has an adjustable input impedance. The device integrates eight LVPECL outputs with adjustable swing/power level and one CML output in 3 dB steps.
Each output stage can be enabled or disabled via hardware control pins or serial port interface controls to conserve power when not needed.
apply
- SONET, Fibre Channel, GigE clock distribution
- ADC/DAC clock distribution
- Low skew and jitter clock or data fan-out
- Wireless/wired communication
- Level shifting
- High-performance instrumentation
- Medical imaging
- Single-ended to differential conversion