The AD9684 is a dual, 14-bit, 500 MSPS ADC. The device includes an on-chip buffer and sample-and-hold circuitry designed for low power, small size, and ease of use. This product is used to sample wide bandwidth analog signals. The AD9684 is optimized for wide input bandwidth, high sample rate, excellent linearity, and low power consumption in a small package.
This dual ADC core uses a multistage, differential pipelined architecture with integrated output error correction logic. Each ADC has wide-bandwidth buffered inputs that support a variety of user-selectable input ranges. An integrated reference simplifies design. The data outputs of each ADC are internally connected to an optional 1/2 decimation block.
Both the analog input and the clock signal are differential. Each ADC data output is internally connected to two digital downconverters (DDCs). Each DDC contains four cascaded signal processing stages: a 12-bit frequency converter (NCO) and three half-band decimation filters supporting divide-by-2, 4, and 8.
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- correspondence
- Diversity multiband, multimode digital receiver
3G/4G、TD-SCDMA、WCDMA、MC-GSM、LTE
- Universal software defined radio
- Ultra-wideband satellite receiver
- Instrumentation (spectrum analyzers, network analyzers, integrated RF test solutions)
- radar
- Digital oscilloscope
- High-speed data acquisition system
- DOCSIS CMTS upstream receive path
- HFC digital reverse path receiver