ADC08500CIYB

• Internal sampling and holding
• Single +1.9 V ± 0.1 V operation
• Choice of SDR or DDR output clock
• Multiple ADC synchronization capability
• No code loss guaranteed
• Serial interface for extended control
• Enter fine-tuning and offset for the full-scale range
• Duty cycle corrects the sampling clock

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ADC08500 is a low-power, high-performance CMOS analog-to-digital converter with 8-bit digitized signals and a sampling rate of up to 500 MSPS resolution. Consuming a typical 0.8 watt from a single 1.9 volt supply at 500 MSPS, this device is guaranteed to be code-free over the entire operating temperature range. The unique folding and interpolation architecture, the design of the fully differential comparator, the internal sampling with hold amplifier and self-calibration plan make an innovative design that responds very flat to all dynamic parameters except Nyquist, producing an input signal with a high ENOB of 7.5 MHz and a sampling rate of 500 MHz while providing 10 -18 The BER output format is offset binary, with an adjustable common-mode voltage anomaly between 0.8V and 1.2V, and the LVDS digital output is IEEE 1596.3-1996 compliant.

The converter features a 1:2 demultiplexer, feeding two LVDS buses, and the output data rate on each bus is reduced by half the sample rate.

The typical power consumption of the power-down mode converter is less than 3.5 megawatts and 128 leads, and the heat-resistant reinforced exposed pad LQFP package is packaged in an industrial (-40°C). ≤ T A ≤ 85°C) temperature range.

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• Direct RF downconversion
• Digital oscilloscope
• Satellite set-top box
• Communication system
• Test instruments