ADC08500CIYB

• Internal sampling and holding
• Single +1.9 V ± 0.1 V operation
• Choice of SDR or DDR output clock
• Multiple ADC synchronization capabilities
• No missing codes are guaranteed
• Serial interface for extended control
• Enter fine-tuning and offset over the full-scale range
• Duty cycle correction sample clock

illustrate

The ADC08500 is a low power, high performance CMOS analog-to-digital converter that digitizes 8-bit signals and samples up to 500 MSPS. At 500 MSPS consuming a typical 0.8 watt from a single 1.9 volt power supply, this device is guaranteed no missing codes over the entire operating temperature range. The unique folded and interpolated architecture, fully differential comparator design, internal sample-and-hold amplifier and self-calibration program enable an innovative design that responds very flat to all dynamic parameters other than Nyquist, producing an input signal with an ENOB of 250 MHz of high 7.5 and a sample rate of 500 MHz while delivering 10 -18 The BER output format is offset binary code, with an adjustable common-mode voltage anomaly between 0.8V and 1.2V, and the LVDS digital output is IEEE 1596.3-1996 compliant.

The converter has a 1:2 demultiplexer that feeds two LVDS buses, and the output data rate on each bus is reduced by half the sample rate.

Typical power consumption in power-down mode converters is less than 3.5 MW and 128 leads, and the heat-resistant enhanced exposed pad LQFP package is available in an industrial (-40°C). ≤ _TA ≤ 85°C) temperature range.

Main specifications

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• Direct RF downconversion
• Digital oscilloscope
• Satellite set-top box
• Communication systems
• Test instruments