DS90CF386MTD

• There is no special boot sequence between the required clock/data/PD pins. Can be applied to input signals (clock and data) to power devices before or after.
• It supports frequency modulation of spread spectrum clocks up to 100KHz and ± 2.5% center spread or -5% deviation with downward spread.
• The "Input Clock Detection" function will pull all LVDS pairs when the logic is low, the input clock is lost and the /PD pin is logic high.
• Shift clock support from 18 to 68 MHz
• The best class settings and keep TxINPUTs in the time
• 发射功率消耗
• BiCMOS replaces 40% of the power dissipation
• TX掉电模式
• Supports VGA, SVGA, XGA, and SXGA with dual pixels.
• The narrow bus reduces the size and cost of the cable
• Up to 1.8 Gbps throughput
• Up to 227 megabytes per second of bandwidth
• 345 mV (typical) low EMI for swinging LVDS devices
• PLLs do not require external components
• Compatible with TIA/EIA-644 LVDS standards
• Low-profile 56-pin TSSOP package
• Improvements: SN75LVDS83, DS90CF383A replaced

illustrate

CMOS/TTL data DS90CF383B transmitter to 4 LVDS (Low Voltage Differential Signaling) data streams is converted to 28 bits. A phase-locked send clock is the parallel data streaming of more than one-fifth of the LVDS links. For each transmit clock cycle, 28-bit input data is sampled and transmitted. Transmit clock frequencies at 65 MHz, 24-bit RGB data and 3-bit LCD timing and control data (FPLINE, FPFRAME, DRDY) at 455 Mbps per LVDS data channel speed. It uses a 65 MHz clock and has a data throughput of 227 MB/s. DS90CF383B is a fixed drop-edge strobe transmitter and will interoperate with a drop-edge strobe receiver without any conversion logic (DS90CF386).

This chipset is an ideal means to solve problems related to EMI and wide-cable, high-speed TTL interfaces.