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There is no special boot order between the required clock/data/PD pins. Can be applied to input signals (clock and data) to power the device before or after.
- Supports frequency modulation of spread spectrum clocks up to 100KHz and ± 2.5% center spread or -5% deviation, downspread.
- The "Input Clock Detection" function pulls all LVDS to logic low when the input clock is lost and the /PD pin is logic high.
- Shift clock support from 18 to 68 MHz
- The best class settings and keep TxINPUTS in the times
- Transmit power consumption
- Less than 40% of the power dissipation is replaced by BiCMOS
- TX power-down mode
- Supports VGA, SVGA, XGA, and dual-pixel SXGA.
- The narrow bus reduces the size and cost of the cable
- Up to 1.8 Gbps throughput
- Up to 227 megabytes per second bandwidth
- Low EMI of 345 millivolts (typical) oscillating LVDS devices
- The PLL requires no external components
- Compatible with the TIA/EIA-644 LVDS standard
- Low profile 56-pin TSSOP package
- Improved: SN75LVDS83, DS90CF383A replacement
illustrate
The DS90CF383B transmitter converts CMOS/TTL data to four LVDS (low voltage differential signaling) data streams to 28 bits. A phase-locked transmit clock is more than one-fifth of the parallel traffic transmission of the LVDS link. Each transmit clock cycle, 28-bit input data is sampled and transmitted. TRANSMITTING CLOCK FREQUENCY AT 65 MEGAHERTZ, 24-BIT RGB DATA AND 3-BIT LCD TIMING AND CONTROL DATA (FPLINE, FPFRAME, DRDY) AT A SPEED OF 455 MBS PER LVDS DATA CHANNEL. With a 65 MHz clock, the data throughput is 227 MB/s. The DS90CF383B is a fixed falling edge strobe transmitter and interoperates with a falling edge strobe receiver without any conversion logic (DS90CF386).
This chipset is an ideal solution to issues related to EMI and cable size wide, high-speed TTL interfaces.
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