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DS90CR486VSX
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DS90CR486VSX

  • Category:Serializer-deserializer
  • Product Name:Deserializer
  • Manufacturers:NSC
  • Production Batch Number:09+
  • Encapsulation:TQFP
  • Stock Status:There is stock
  • Stock Quantity:3000
  • Minimum order quantity: 1
  • Details:Click here to find PDF information on the DS90CR486VSX
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  • Product introduction

peculiarity

  • Up to 6.384 Gbps throughput
  • 66MHz to 133MHz input clock support
  • Reduce the size and cost of cables and connectors
  • Cable guiding function
  • DC balancing reduces ISI distortion
  • For point-to-point backplane or cable applications
  • Low power consumption, typical at 890 mW at 133MHz
  • Simple PCB design flow with pinouts
  • +3.3 V supply voltage
  • 100-pin TQFP package
  • Complies with TIA/EIA-644-A-2001 LVDS standards

illustrate

The DS90CR486 receives eight low-voltage differential signaling (LVDS) streams back to 48-bit LVCMOS/LVTTL data conversion. With a clock of 133MHz, the data throughput is 6.384Gbit/s (798Mbytes/s).

Data line multiplexing provides a significant amount of cable reduction. Long-distance parallel single-ended buses typically require each aggressive signal ground with very limited noise rejection. Therefore, for a 48-bit wide data and clock, up to 98 conductors are required. With this channel link, a chipset with a number of 19 conductors (8 data pairs, 1 clock pair and the lowest of one place) is necessary. This provides an 80% reduction in interconnect width, which provides a system cost savings, reduces the physical size and cost of connectors, and reduces shielding requirements due to smaller cable profiles.

The DS90CR486 deserializer is an improvement over previous generations of channel connectivity devices and provides higher bandwidth support and longer cable drivers with three areas enhanced. Increased bandwidth, maximum clock rate increased to 133 MHz and 8 serialized LVDS outputs are provided. The cable driver has enhanced user-selectable pre-emphasis (on the DS90CR485) to provide additional output current to offset cable loading effects during conversion. Optional DC is also available for balancing on a cycle basis, reducing ISI (intersymbol interference). With pre-emphasis and DC balancing, the low-distortion eye diagram is on the receiving end of the cable. Cable guiding has been added to guide long cable pair skew. These enhancements allow long cables to be driven.

The DS90CR486 is intended for use with the DS90CR485 channel link serial. It is also backward compatible with serialized DS90CR481 and DS90CR483. The DS90CR486 is footprint compatible with the DS90CR484.

The chipset is an ideal solution to address the size of EMI and point-to-point applications with high throughput interconnects.

For more information, see the Application Information section in this datasheet.

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