ADN4670is a low-voltage differential signal (LVDS)
Clock driver, one differential clock input signal can be extended to ten differential clock outputs. The device can be programmed through a simple serial interface to select one of two clock inputs (CLK0/
CLK0 or CLK1/
CLK1), and enable or disable (tri-state) any differential output (Q0/
Q0to Q9/
Q9) 。 The ADN4670 is designed for use in 50 Ω transmission line environments.
When the enable input EN is high, the device can be programmed by entering 11 data bits into the shift register. The first 10 bits determine which outputs are enabled (0 = disabled, 1 = enabled), and the 11th bit selects the clock input (0 = CLK0, 1 = CLK1). The 12th clock pulse transfers data from the shift register to the control register.
The ADN4670 is specified over the industrial temperature range and is available in a 32-lead LFCSP package.
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Clock distribution network