The HMC848LC5 is a 1:4 demultiplexer designed for data deserialization applications up to 45 Gbps. The device uses the rising and falling edges of the half-rate clock to sample the input data sequences D0-D3 and latch the data to the differential output. An on-chip 1/4 rate clock output signal is generated that can be used to read data into other devices.
All of the HMC848LC5clockand data input/output are CML and terminated to VCC via on-chip 50 Ω, either DC or AC coupled. The inputs and outputs of the HMC848LC5 can operate in differential or single-ended configurations. The HMC848LC5 also integrates an output level control pin, VCTRL, which can be used for loss compensation or signal level optimization. The HMC848LC5 operates from a single +3.3V supply and is available in a ROHS-compliant 5x5 mm SMT package.
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- SONET OC-768
- RF ATE applications
- Broadband test and measurement
- Serial data transmission up to 45 Gbps
- High speed ADC interface