HMC848LC5 is a 1:4 deplexer designed for up to 45 Gbps data deserialization applications. The device uses the rising and falling edges of a half-rate clock to sample the input data sequence D0-D3 and latch the data to the differential output. A 1/4 rate clock output signal is generated on-chip that can be used to read data to other devices.
All clock and data inputs/outputs of the HMC848LC5 are CML and terminated to VCC via an on-chip 50 Ω, which can be DC or AC coupled. HMC848LC5 inputs and outputs can be operated in differential or single-ended configurations. HMC848LC5 also integrates an output level control pin, VCTRL, which can be used for loss compensation or signal level optimization. HMC848LC5 operates from a single +3.3V supply and is available in a ROHS-compliant 5x5 mm SMT package.
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SONET OC-768
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RF ATE应用
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宽带测试和测量
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串行数据传输高达45 Gbps
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高速ADC接口